| Patent | Date |
|---|
Zone polishing using variable slurry solid content
Grant 7,163,438 - Maury , et al. January 16, 2 | 2007-01-16 |
Zone polishing using variable slurry solid content
Grant 6,984,166 - Maury , et al. January 10, 2 | 2006-01-10 |
Multi-layered semiconductor structure
Grant 6,977,128 - Boulin , et al. December 20, 2 | 2005-12-20 |
Zone polishing using variable slurry solid content
App 20050277372 - Maury, Alvaro ; et al. | 2005-12-15 |
Contact for use in an integrated circuit and a method of manufacture therefor
Grant 6,910,907 - Layadi , et al. June 28, 2 | 2005-06-28 |
Method to monitor silicide formation on product wafers
App 20050134857 - Maury, Alvaro ; et al. | 2005-06-23 |
Trench isolation structure and method of manufacture therefor
App 20050106835 - Layadi, Nace ; et al. | 2005-05-19 |
Contact For Use In An Integrated Circuit And A Method Of Manufacture Therefor
App 20050106919 - Layadi, Nace ; et al. | 2005-05-19 |
Zone polishing using variable slurry solid content
App 20050026549 - Maury, Alvaro ; et al. | 2005-02-03 |
IMP TiN barrier metal process
Grant 6,821,886 - Layadi , et al. November 23, 2 | 2004-11-23 |
Multi-layered semiconductor structure
App 20040094847 - Boulin, David M. ; et al. | 2004-05-20 |
Method of dry etching a semiconductor device in the absence of a plasma
Grant 6,730,600 - Layadi , et al. May 4, 2 | 2004-05-04 |
Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
Grant 6,727,588 - Abdelgadir , et al. April 27, 2 | 2004-04-27 |
Capacitor for an integrated circuit
Grant 6,720,604 - Fritzinger , et al. April 13, 2 | 2004-04-13 |
Method Of Dry Etching A Semiconductor Device In The Absence Of A Plasma
App 20040063315 - Layadi, Nace ; et al. | 2004-04-01 |
Method of forming an alignment feature in or on a multi-layered semiconductor structure
Grant 6,706,609 - Boulin , et al. March 16, 2 | 2004-03-16 |
Method for metal patterning and improved linewidth control
App 20030228755 - Esry, Thomas Craig ; et al. | 2003-12-11 |
Method for in-situ removal of side walls in MOM capacitor formation
Grant 6,656,850 - Molloy , et al. December 2, 2 | 2003-12-02 |
Method of forming an alignment feature in or on a multilayered semiconductor structure
Grant 6,576,529 - Boulin , et al. June 10, 2 | 2003-06-10 |
Method For Reducing A Metal Seam In An Interconnect Structure And A Device Manufactured Thereby
App 20030038369 - Layadi, Nace ; et al. | 2003-02-27 |
Method for in-situ removal of side walls in MOM capacitor formation
App 20020192897 - Molloy, Simon J. ; et al. | 2002-12-19 |
Polish or etch stop layer
App 20020180052 - Layadi, Nace ; et al. | 2002-12-05 |
Semiconductor device having reduced line width variations between tightly spaced and isolated features
Grant 6,406,999 - Esry , et al. June 18, 2 | 2002-06-18 |
Method for cleaning tungsten from deposition wall chambers
App 20020062846 - Layadi, Nace ; et al. | 2002-05-30 |
Method of forming an alignment feature in or on a multi-layered semiconductor structure
App 20020004283 - Boulin, David M. ; et al. | 2002-01-10 |
Method analyzing a semiconductor surface using line width metrology with auto-correlation operation
Grant 6,258,610 - Blatchford , et al. July 10, 2 | 2001-07-10 |
Method of making a capacitor
Grant 6,218,255 - Fritzinger , et al. April 17, 2 | 2001-04-17 |
Method of making integrated circuit capacitor including tapered plug
Grant 6,204,186 - Chaudhry , et al. March 20, 2 | 2001-03-20 |
Method for forming vias in a low dielectric constant material
Grant 6,180,518 - Layadi , et al. January 30, 2 | 2001-01-30 |
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