Lauer; Gen P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lauer; Gen P..The latest application filed is for "enhanced coercivity in mtj devices by contact depth control".

Company Profile

8.47.41

Lauer; Gen P. - Yorktown Heights NY
Lauer; Gen P. - Mahopac NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Enhanced coercivity in MTJ devices by contact depth control Grant 11,011,698 - Annunziata , et al. May 18, 2	2021-05-18
Enhanced coercivity in MTJ devices by contact depth control Grant 10,497,862 - Annunziata , et al. De	2019-12-03
Spin torque MRAM fabrication using negative tone lithography and ion beam etching Grant 10,388,857 - Annunziata , et al. A	2019-08-20
Structure and method to reduce shorting and process degradation in stt-MRAM devices Grant 10,256,397 - Annunziata , et al.	2019-04-09
Structure and method to reduce shorting and process degradation in STT-MRAM devices Grant 10,243,138 - Annunziata , et al.	2019-03-26
Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FET Grant 10,170,609 - Cheng , et al. J	2019-01-01
Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET Grant 10,170,608 - Cheng , et al. J	2019-01-01
Spin torque MRAM fabrication using negative tone lithography and ion beam etching Grant 10,170,698 - Annunziata , et al. J	2019-01-01
Enhanced Coercivity In Mtj Devices By Contact Depth Control App 20180309053 - Annunziata; Anthony J. ; et al.	2018-10-25
Enhanced coercivity in MTJ devices by contact depth control Grant 10,084,127 - Annunziata , et al. September 25, 2	2018-09-25
Structure And Method To Reduce Shorting And Process Degradation In Stt-mram Devices App 20180190901 - Annunziata; Anthony J. ; et al.	2018-07-05
Structure And Method To Reduce Shorting And Process Degradation In Stt-mram Devices App 20180190900 - Annunziata; Anthony J. ; et al.	2018-07-05
Structure and method to reduce shorting and process degradation in STT-MRAM devices Grant 9,960,347 - Annunziata , et al. May 1, 2	2018-05-01
Stacked planar double-gate lamellar field-effect transistor Grant 9,954,063 - Chang , et al. April 24, 2	2018-04-24
Stacked planar double-gate lamellar field-effect transistor Grant 9,954,062 - Chang , et al. April 24, 2	2018-04-24
Structure and method to reduce shorting in STT-MRAM device Grant 9,947,863 - Annunziata , et al. April 17, 2	2018-04-17
Stacked planar double-gate lamellar field-effect transistor Grant 9,859,375 - Chang , et al. January 2, 2	2018-01-02
Reduced process degradation of spin torque magnetoresistive random access memory Grant 9,853,210 - Annunziata , et al. December 26, 2	2017-12-26
III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology Grant 9,812,370 - Chang , et al. November 7, 2	2017-11-07
Structure and method to reduce shorting in STT-MRAM device Grant 9,748,310 - Annunziata , et al. August 29, 2	2017-08-29
Spin Torque Mram Fabrication Using Negative Tone Lithography And Ion Beam Etching App 20170244024 - Annunziata; Anthony J. ; et al.	2017-08-24
Structure And Method To Reduce Shorting And Process Degradation In Stt-mram Devices App 20170229641 - Annunziata; Anthony J. ; et al.	2017-08-10
Structure And Method To Reduce Shorting In Stt-mram Device App 20170222134 - Annunziata; Anthony J. ; et al.	2017-08-03
Enhanced Coercivity In Mtj Devices By Contact Depth Control App 20170222136 - Annunziata; Anthony J. ; et al.	2017-08-03
Enhanced Coercivity In Mtj Devices By Contact Depth Control App 20170222130 - Annunziata; Anthony J. ; et al.	2017-08-03
Spin torque MRAM fabrication using negative tone lithography and ion beam etching Grant 9,705,077 - Annunziata , et al. July 11, 2	2017-07-11
Structure and method to reduce shorting and process degradation in STT-MRAM devices Grant 9,705,071 - Annunziata , et al. July 11, 2	2017-07-11
Enhancement Of Spin Transfer Torque Magnetoresistive Random Access Memory Device Using Hydrogen Plasma App 20170186944 - Annunziata; Anthony J. ; et al.	2017-06-29
Low temperature encapsulation for magnetic tunnel junction Grant 9,691,972 - Annunziata , et al. June 27, 2	2017-06-27
Low Temperature Encapsulation For Magnetic Tunnel Junction App 20170179194 - Annunziata; Anthony J. ; et al.	2017-06-22
Structure and method to reduce shorting in STT-MRAM device Grant 9,673,386 - Annunziata , et al. June 6, 2	2017-06-06
Structure And Method To Reduce Shorting And Process Degradation In Stt-mram Devices App 20170148976 - Annunziata; Anthony J. ; et al.	2017-05-25
Enhanced coercivity in MTJ devices by contact depth control Grant 9,660,179 - Annunziata , et al. May 23, 2	2017-05-23
Reduced Process Degradation Of Spin Torque Magnetoresistive Random Access Memory App 20170141299 - Annunziata; Anthony J. ; et al.	2017-05-18
Magnetoresistive structures with stressed layer Grant 9,653,679 - Annunziata , et al. May 16, 2	2017-05-16
Structure And Method To Reduce Shorting In Stt-mram Device App 20170125667 - Annunziata; Anthony J. ; et al.	2017-05-04
Structure And Method To Reduce Shorting In Stt-mram Device App 20170125480 - Annunziata; Anthony J. ; et al.	2017-05-04
Magnetoresistive structures with stressed layer Grant 9,601,686 - Annunziata , et al. March 21, 2	2017-03-21
Spin Torque Mram Fabrication Using Negative Tone Lithography And Ion Beam Etching App 20170062707 - Annunziata; Anthony J. ; et al.	2017-03-02
Spin Torque Mram Fabrication Using Negative Tone Lithography And Ion Beam Etching App 20170062708 - Annunziata; Anthony J. ; et al.	2017-03-02
III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology App 20170040219 - Chang; Josephine B. ; et al.	2017-02-09
Complementary metal-oxide silicon having silicon and silicon germanium channels Grant 9,543,388 - Lauer , et al. January 10, 2	2017-01-10
Internal Spacer Formation From Selective Oxidation For Fin-first Wire-last Replacement Gate-all-around Nanowire Fet App 20170005180 - Cheng; Szu-Lin ; et al.	2017-01-05
Internal Spacer Formation From Selective Oxidation For Fin-first Wire-last Replacement Gate-all-around Nanowire Fet App 20170005188 - Cheng; Szu-Lin ; et al.	2017-01-05
Low degradation MRAM encapsulation process using silicon-rich silicon nitride film Grant 9,515,252 - Annunziata , et al. December 6, 2	2016-12-06
Structure and method to reduce shorting in STT-MRAM device Grant 9,502,640 - Annunziata , et al. November 22, 2	2016-11-22
III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology Grant 9,496,184 - Chang , et al. November 15, 2	2016-11-15
Structure and method to reduce shorting in STT-MRAM device Grant 9,450,180 - Annunziata , et al. September 20, 2	2016-09-20
Stacked Planar Double-gate Lamellar Field-effect Transistor App 20160233314 - Chang; Josephine B. ; et al.	2016-08-11
Stacked Planar Double-gate Lamellar Field-effect Transistor App 20160233320 - Chang; Josephine B. ; et al.	2016-08-11
Stacked Planar Double-gate Lamellar Field-effect Transistor App 20160233304 - Chang; Josephine B. ; et al.	2016-08-11
Complementary Metal-oxide Silicon Having Silicon And Silicon Germanium Channels App 20160211328 - Lauer; Gen P. ; et al.	2016-07-21
Complementary Metal-oxide Silicon Having Silicon And Silicon Germanium Channels App 20160211327 - Lauer; Gen P. ; et al.	2016-07-21
Magnetic tunnel junction with post-deposition hydrogenation Grant 9,397,287 - Annunziata , et al. July 19, 2	2016-07-19
Stacked planar double-gate lamellar field-effect transistor Grant 9,391,163 - Chang , et al. July 12, 2	2016-07-12
Complementary metal-oxide silicon having silicon and silicon germanium channels Grant 9,373,638 - Lauer , et al. June 21, 2	2016-06-21
Stacked Planar Double-gate Lamellar Field-effect Transistor App 20160099338 - Chang; Josephine B. ; et al.	2016-04-07
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor Grant 9,240,324 - BrightSky , et al. January 19, 2	2016-01-19
III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method Grant 9,209,095 - Chang , et al. December 8, 2	2015-12-08
Low temperature salicide for replacement gate nanowires Grant 9,209,086 - Chang , et al. December 8, 2	2015-12-08
Iii-v, Ge, Or Sige Fin Base Lateral Bipolar Transistor Structure And Method App 20150287650 - Chang; Josephine B. ; et al.	2015-10-08
III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology App 20150287642 - Chang; Josephine B. ; et al.	2015-10-08
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor Grant 9,012,970 - BrightSky , et al. April 21, 2	2015-04-21
Low Temperature Salicide for Replacement Gate Nanowires App 20150021715 - Chang; Josephine B. ; et al.	2015-01-22
High-rate chemical vapor etch of silicon substrates Grant 8,927,431 - Bedell , et al. January 6, 2	2015-01-06
High-Rate Chemical Vapor Etch of Silicon Substrates App 20140357082 - Bedell; Stephen W. ; et al.	2014-12-04
Self-aligned Process To Fabricate A Memory Cell Array With A Surrounding-gate Access Transistor App 20140322907 - BrightSky; Matthew J. ; et al.	2014-10-30
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor Grant 8,853,662 - BrightSky , et al. October 7, 2	2014-10-07
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor Grant 8,835,898 - BrightSky , et al. September 16, 2	2014-09-16
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor Grant 8,673,717 - BrightSky , et al. March 18, 2	2014-03-18
Self-aligned Process To Fabricate A Memory Cell Array With A Surrounding-gate Access Transistor App 20140061581 - BrightSky; Matthew J. ; et al.	2014-03-06
Self-aligned Process To Fabricate A Memory Cell Array With A Surrounding-gate Access Transistor App 20140021533 - BrightSky; Matthew J. ; et al.	2014-01-23
Self-aligned Process To Fabricate A Memory Cell Array With A Surrounding-gate Access Transistor App 20140024185 - BrightSky; Matthew J. ; et al.	2014-01-23
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor Grant 8,614,117 - BrightSky , et al. December 24, 2	2013-12-24
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor Grant 8,592,250 - BrightSky , et al. November 26, 2	2013-11-26
Self-aligned Process To Fabricate A Memory Cell Array With A Surrounding-gate Access Transistor App 20130277639 - BrightSky; Matthew J. ; et al.	2013-10-24
Self-aligned Process To Fabricate A Memory Cell Array With A Surrounding-gate Access Transistor App 20130200330 - BrightSky; Matthew J. ; et al.	2013-08-08
Self-aligned Process To Fabricate A Memory Cell Array With A Surrounding-gate Access Transistor App 20130193401 - BrightSky; Matthew J. ; et al.	2013-08-01

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.