Lau; Te-Li

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lau; Te-Li.The latest application filed is for "high-performance, superscalar-based computer system with out-of-order instruction execution".

Company Profile

0.38.19

Lau; Te-Li - Palo Alto CA
Lau; Te-Li - Palto Alto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for handling load and/or store operations in a superscalar microprocessor Grant 8,019,975 - Brashears , et al. September 13, 2	2011-09-13
High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution Grant 7,941,635 - Nguyen , et al. May 10, 2	2011-05-10
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,739,482 - Nguyen , et al. June 15, 2	2010-06-15
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,721,070 - Nguyen , et al. May 18, 2	2010-05-18
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 7,657,712 - Lentz , et al. February 2, 2	2010-02-02
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 7,555,632 - Nguyen , et al. June 30, 2	2009-06-30
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,487,333 - Nguyen , et al. February 3, 2	2009-02-03
High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution App 20090019261 - NGUYEN; Le Trong ; et al.	2009-01-15
High-performance, superscalar-based computer system with out-of-order instruction execution App 20070106878 - Nguyen; Le Trong ; et al.	2007-05-10
High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution App 20070101103 - Nguyen; Le Trong ; et al.	2007-05-03
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,162,610 - Nguyen , et al. January 9, 2	2007-01-09
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution App 20060149925 - Nguyen; Le Trong ; et al.	2006-07-06
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 7,028,161 - Nguyen , et al. April 11, 2	2006-04-11
Microprocessor architecture capable of supporting multiple heterogeneous processors App 20060064569 - Lentz; Derek J. ; et al.	2006-03-23
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,986,024 - Nguyen , et al. January 10, 2	2006-01-10
System and method for handling load and/or store operations in a superscalar microprocessor App 20050283591 - Brashears, Cheryl Senter ; et al.	2005-12-22
System and method for handling load and/or store operations in a superscalar microprocessor Grant 6,965,987 - Senter Brashears , et al. November 15, 2	2005-11-15
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,959,375 - Nguyen , et al. October 25, 2	2005-10-25
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 6,954,844 - Lentz , et al. October 11, 2	2005-10-11
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,948,052 - Nguyen , et al. September 20, 2	2005-09-20
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,941,447 - Nguyen , et al. September 6, 2	2005-09-06
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,934,829 - Nguyen , et al. August 23, 2	2005-08-23
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,915,412 - Nguyen , et al. July 5, 2	2005-07-05
System and method for handling load and/or store operations in a superscalar microprocessor App 20040128487 - Brashears, Cheryl Senter ; et al.	2004-07-01
High performance, superscalar-based computer system with out-of-order instruction execution App 20040093483 - Nguyen, Le Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order instruction execution App 20040093482 - Nguyen, Le-Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order instruction execution App 20040093485 - Nguyen, Le Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order intstruction execution App 20040054872 - Nguyen, Le Trong ; et al.	2004-03-18
Microprocessor architecture capable of supporting multiple heterogeneous processors App 20040024987 - Lentz, Derek J. ; et al.	2004-02-05
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,647,485 - Nguyen , et al. November 11, 2	2003-11-11
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 6,611,908 - Lentz , et al. August 26, 2	2003-08-26
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030079113 - Nguyen, Le Trong ; et al.	2003-04-24
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030070060 - Nguyen, Le Trong ; et al.	2003-04-10
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030056087 - Nguyen, Le Trong ; et al.	2003-03-20
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030056086 - Nguyen, Le Trong ; et al.	2003-03-20
Microprocessor architecture capable of supporting multiple heterogeneous processors App 20020059508 - Lentz, Derek J. ; et al.	2002-05-16
High-performance, superscalar-based computer system with out-of-order instruction execution App 20020029328 - Nguyen, Le Trong ; et al.	2002-03-07
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution App 20020016903 - Nguyen, Le Trong ; et al.	2002-02-07
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 6,282,630 - Nguyen , et al. August 28, 2	2001-08-28
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,272,619 - Nguyen , et al. August 7, 2	2001-08-07
Microprocessor architecture capable of supporting multiple heterogeneous processors Grant 6,272,579 - Lentz , et al. August 7, 2	2001-08-07
High performance, superscalar-based computer system with out-of-order instruction execution Grant 6,256,720 - Nguyen , et al. July 3, 2	2001-07-03
System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit Grant 6,219,763 - Lentz , et al. April 17, 2	2001-04-17
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,128,723 - Nguyen , et al. October 3, 2	2000-10-03
High performance, superscalar-based computer system with out-of-order instruction execution Grant 6,038,654 - Nguyen , et al. March 14, 2	2000-03-14
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 6,038,653 - Nguyen , et al. March 14, 2	2000-03-14
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 5,832,292 - Nguyen , et al. November 3, 1	1998-11-03
Compression and decompression scheme performed on shared workstation memory by media coprocessor Grant 5,768,445 - Troeller , et al. June 16, 1	1998-06-16
Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption Grant 5,754,800 - Lentz , et al. May 19, 1	1998-05-19
High-performance superscalar-based computer system with out-of-order instruction execution Grant 5,689,720 - Nguyen , et al. November 18, 1	1997-11-18
Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU Grant 5,604,865 - Lentz , et al. February 18, 1	1997-02-18
Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units Grant 5,564,117 - Lentz , et al. October 8, 1	1996-10-08
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 5,560,032 - Nguyen , et al. September 24, 1	1996-09-24
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 5,539,911 - Nguyen , et al. July 23, 1	1996-07-23
Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU Grant 5,440,752 - Lentz , et al. August 8, 1	1995-08-08
Page printer controller including a single chip superscalar microprocessor with graphics functional units Grant 5,394,515 - Lentz , et al. February 28, 1	1995-02-28
Semaphore bypass Grant 5,261,106 - Lentz , et al. November 9, 1	1993-11-09

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