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name:-0.010410070419312
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Lau; Ker Yon Patent Filings

Lau; Ker Yon

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lau; Ker Yon.The latest application filed is for "zero-offset sampling for clock duty cycle correction".

Company Profile
1.9.3
  • Lau; Ker Yon - Pearl Island MY
  • Lau; Ker Yon - Bayan Lepas MY
  • Lau; Ker Yon - Setia Pearl Island MY
  • Lau; Ker Yon - My MY
  • Lau; Ker Yon - Penang MY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dual signal protocol input/output (I/O) buffer circuit
Grant 10,224,911 - Tan , et al.
2019-03-05
Aging-resistant signal path circuitry
Grant 10,110,229 - Lau October 23, 2
2018-10-23
Integrated circuit with an increased signal bandwidth input/output (I/O) circuit
Grant 10,110,225 - Lau , et al. October 23, 2
2018-10-23
Transmitter driver circuits and methods
Grant 9,948,293 - Lau April 17, 2
2018-04-17
Zero-offset sampling for clock duty cycle correction
Grant 9,941,871 - Lau April 10, 2
2018-04-10
Zero-offset Sampling For Clock Duty Cycle Correction
App 20180091128 - Lau; Ker Yon
2018-03-29
High-voltage tolerant input voltage buffer circuit
Grant 9,608,636 - Lau March 28, 2
2017-03-28
Voltage level shift with charge pump assist
Grant 9,391,600 - Lau July 12, 2
2016-07-12
High-voltage Tolerant Input Voltage Buffer Circuit
App 20160197613 - LAU; Ker Yon
2016-07-07
Voltage Level Shift With Charge Pump Assist
App 20150288355 - Lau; Ker Yon
2015-10-08
Techniques for capturing signals at output pins in a programmable logic integrated circuit
Grant 7,406,642 - Lau July 29, 2
2008-07-29

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