| Patent | Date |
|---|
Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch
Grant 7,989,358 - Daubenspeck , et al. August 2, 2 | 2011-08-02 |
Deep trench contact and isolation of buried photodetectors
Grant 7,652,313 - Ellis-Monaghan , et al. January 26, 2 | 2010-01-26 |
Recessed gate for a CMOS image sensor
Grant 7,572,701 - Adkisson , et al. August 11, 2 | 2009-08-11 |
Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices
Grant 7,495,254 - Fales , et al. February 24, 2 | 2009-02-24 |
Method of forming pixel sensor cell having reduced pinning layer barrier potential
Grant 7,459,360 - Adkisson , et al. December 2, 2 | 2008-12-02 |
Prevention Of Backside Cracks In Semiconductor Chips Or Wafers Using Backside Film Or Backside Wet Etch
App 20080191322 - Daubenspeck; Timothy H. ; et al. | 2008-08-14 |
Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch
Grant 7,405,139 - Daubenspeck , et al. July 29, 2 | 2008-07-29 |
Prevention Of Backside Cracks In Semiconductor Chips Or Wafers Using Backside Film Or Backside Wet Etch
App 20080122037 - Daubenspeck; Timothy H. ; et al. | 2008-05-29 |
Recessed Gate For A Cmos Image Sensor
App 20070184614 - Adkisson; James W. ; et al. | 2007-08-09 |
Pixel Sensor Cell Having Reduced Pinning Layer Barrier Potential And Method Thereof
App 20070145438 - Adkisson; James W. ; et al. | 2007-06-28 |
Recessed gate for an image sensor
Grant 7,217,968 - Adkisson , et al. May 15, 2 | 2007-05-15 |
Deep Trench Contact And Isolation Of Buried Photodetectors
App 20070102740 - Ellis-Monaghan; John J. ; et al. | 2007-05-10 |
Pixel sensor cell having reduced pinning layer barrier potential and method thereof
Grant 7,205,591 - Adkisson , et al. April 17, 2 | 2007-04-17 |
Test Structure And Method For Detecting And Studying Crystal Lattice Dislocation Defects In Integrated Circuit Devices
App 20070051948 - Fales; Jonathan R. ; et al. | 2007-03-08 |
Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet
Grant 7,183,573 - Bryant , et al. February 27, 2 | 2007-02-27 |
FIN field effect transistor with self-aligned gate
Grant 7,173,303 - Gambino , et al. February 6, 2 | 2007-02-06 |
Pixel Sensor Cell Having Reduced Pinning Layer Barrier Potential And Method Thereof
App 20060226456 - Adkisson; James W. ; et al. | 2006-10-12 |
Recessed Gate For An Image Sensor
App 20060124976 - Adkisson; James W. ; et al. | 2006-06-15 |
Integrated cobalt silicide process for semiconductor devices
Grant 6,793,735 - Cantell , et al. September 21, 2 | 2004-09-21 |
FIN field effect transistor with self-aligned gate
App 20040092060 - Gambino, Jeffrey P. ; et al. | 2004-05-13 |
Power distribution design method for stacked flip-chip packages
Grant 6,727,118 - Lasky , et al. April 27, 2 | 2004-04-27 |
Fin field effect transistor with self-aligned gate
Grant 6,689,650 - Gambino , et al. February 10, 2 | 2004-02-10 |
Double planar gated SOI MOSFET structure
Grant 6,660,596 - Adkisson , et al. December 9, 2 | 2003-12-09 |
Power distribution design method for stacked flip-chip packages
App 20030209809 - Lasky, Jerome B. ; et al. | 2003-11-13 |
Semiconductor temperature monitor
Grant 6,638,629 - Johnson , et al. October 28, 2 | 2003-10-28 |
Power distribution design method for stacked flip-chip packages
Grant 6,635,970 - Lasky , et al. October 21, 2 | 2003-10-21 |
Power Distribution Design Method For Stacked Flip-chip Packages
App 20030146517 - Lasky, Jerome B. ; et al. | 2003-08-07 |
Method for limiting divot formation in post shallow trench isolation processes
Grant 6,541,351 - Bartlau , et al. April 1, 2 | 2003-04-01 |
Fin field effect transistor with self-aligned gate
App 20030057486 - Gambino, Jeffrey P. ; et al. | 2003-03-27 |
Semiconductor temperature monitor
App 20020176998 - Johnson, Donna K. ; et al. | 2002-11-28 |
Double planar gated SOI MOSFET structure
Grant 6,483,156 - Adkisson , et al. November 19, 2 | 2002-11-19 |
Double planar gated SOI MOSFET structure
App 20020153587 - Adkisson, James W. ; et al. | 2002-10-24 |
SOI devices with integrated gettering structure
App 20020140030 - Mandelman, Jack A. ; et al. | 2002-10-03 |
Disposable spacer for symmetric and asymmetric schottky contact to SOI mosfet
App 20020048841 - Bryant, Andres ; et al. | 2002-04-25 |
Plasma etch pre-silicide clean
Grant 6,255,179 - Cantell , et al. July 3, 2 | 2001-07-03 |
Integrated cobalt silicide process for semiconductor devices
App 20010001298 - Cantell, Marc W. ; et al. | 2001-05-17 |
Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor
Grant 6,038,168 - Allen , et al. March 14, 2 | 2000-03-14 |
Plug strap process utilizing selective nitride and oxide etches
Grant 5,545,581 - Armacost , et al. August 13, 1 | 1996-08-13 |
Semiconductor memory cell and memory array with inversion layer
Grant 5,291,439 - Kauffmann , et al. March 1, 1 | 1994-03-01 |
Emissivity independent temperature measurement systems
Grant 5,226,732 - Nakos , et al. July 13, 1 | 1993-07-13 |
Boron out-diffused surface strap process
Grant 5,185,294 - Lam , et al. February 9, 1 | 1993-02-09 |
Method of self-aligning a trench isolation structure to an implanted well region
Grant 4,799,990 - Kerbaugh , et al. January 24, 1 | 1989-01-24 |
Method of forming metal-strapped polysilicon gate electrode for FET device
Grant 4,755,478 - Abernathey , et al. July 5, 1 | 1988-07-05 |
Method of improving silicon-on-insulator uniformity
Grant 4,735,679 - Lasky April 5, 1 | 1988-04-05 |
Method of fabricating silicon-on-insulator transistors with a shared element
Grant 4,649,627 - Abernathey , et al. March 17, 1 | 1987-03-17 |
Method of producing a thin silicon-on-insulator layer
Grant 4,601,779 - Abernathey , et al. July 22, 1 | 1986-07-22 |
Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step
Grant 4,558,508 - Kinney , et al. December 17, 1 | 1985-12-17 |
Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer
Grant 4,532,700 - Kinney , et al. August 6, 1 | 1985-08-06 |
Method of laser annealing of subsurface ion implanted regions
Grant 4,379,727 - Hansen , et al. April 12, 1 | 1983-04-12 |
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