Lapidus; Peter D.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Lapidus; Peter D..The latest application filed is for "integrated circuit having programmable voltage level line drivers and method of operation".
- Lapidus; Peter D. - Boulder CO
| Patent | Date |
|---|---|
| Bypass custom array and related method for implementing ROM fixes in a data processor Grant 7,062,598 - Lapidus , et al. June 13, 2 | 2006-06-13 |
| Integrated circuit having programmable voltage level line drivers and method of operation Grant 7,058,823 - Lapidus June 6, 2 | 2006-06-06 |
| Flip flop supporting glitchless operation on a one-hot bus and method Grant 6,975,152 - Lapidus December 13, 2 | 2005-12-13 |
| Method and system for providing a shared write driver Grant 6,975,554 - Lapidus , et al. December 13, 2 | 2005-12-13 |
| Method and system for providing a low power memory array Grant 6,950,366 - Lapidus , et al. September 27, 2 | 2005-09-27 |
| Reduced noise line drivers and method of operation Grant 6,700,401 - Lapidus March 2, 2 | 2004-03-02 |
| Reduced noise line drivers and method of operation App 20020118041 - Lapidus, Peter D. | 2002-08-29 |
| Integrated circuit having programmable voltage level line drivers and method of operation App 20020120878 - Lapidus, Peter D. | 2002-08-29 |
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