Langer; Eckhard

Patent Applications and Registrations

Patent applications and USPTO patent grants for Langer; Eckhard.The latest application filed is for "technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance".

Company Profile

0.11.11

Langer; Eckhard - Radebeul N/A DE
Langer; Eckhard - Dresden DE
Langer, Eckhard - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance Grant 8,575,029 - Meyer , et al. November 5, 2	2013-11-05
Method of forming an alloy in an interconnect structure to increase electromigration resistance Grant 8,329,577 - Lehr , et al. December 11, 2	2012-12-11
Technique For Forming Metal Lines In A Semiconductor By Adapting The Temperature Dependence Of The Line Resistance App 20120088365 - Meyer; Moritz Andreas ; et al.	2012-04-12
Technique for monitoring dynamic processes in metal lines of microstructures Grant 8,118,932 - Buschbeck , et al. February 21, 2	2012-02-21
Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance Grant 8,058,731 - Meyer , et al. November 15, 2	2011-11-15
Method of testing an integrity of a material layer in a semiconductor structure Grant 8,058,081 - Meyer , et al. November 15, 2	2011-11-15
Increasing Electromigration Resistance in an Interconnect Structure of a Semiconductor Device by Forming an Alloy App 20110124189 - Lehr; Matthias ; et al.	2011-05-26
Technique for increasing adhesion of metallization layers by providing dummy vias Grant 7,611,991 - Richter , et al. November 3, 2	2009-11-03
Increasing Electromigration Resistance In An Interconnect Structure Of A Semiconductor Device By Forming An Alloy App 20090197408 - Lehr; Matthias ; et al.	2009-08-06
Technique For Forming Metal Lines In A Semiconductor By Adapting The Temperature Dependence Of The Line Resistance App 20080268265 - Meyer; Moritz Andreas ; et al.	2008-10-30
Method Of Testing An Integrity Of A Material Layer In A Semiconductor Structure App 20080160654 - Meyer; Moritz Andreas ; et al.	2008-07-03
Technique for CD measurement on the basis of area fraction determination Grant 7,335,880 - Langer , et al. February 26, 2	2008-02-26
Semiconductor structure comprising a stress sensitive element and method of measuring a stress in a semiconductor structure Grant 7,311,008 - Langer , et al. December 25, 2	2007-12-25
Technique For Increasing Adhesion Of Metallization Layers By Providing Dummy Vias App 20070123009 - Richter; Ralf ; et al.	2007-05-31
Technique For Monitoring Dynamic Processes In Metal Lines Of Microstructures App 20070044710 - BUSCHBECK; JOERG ; et al.	2007-03-01
Technique for CD measurement on the basis of area fraction determination App 20060219906 - Langer; Eckhard ; et al.	2006-10-05
Semiconductor structure comprising a stress sensitive element and method of measuring a stress in a semiconductor structure App 20050263760 - Langer, Eckhard ; et al.	2005-12-01
Technique for monitoring the state of metal lines in microstructures Grant 6,953,755 - Meyer , et al. October 11, 2	2005-10-11
Technique for monitoring the state of metal lines in microstructures App 20050072919 - Meyer, Moritz Andreas ; et al.	2005-04-07
Interface void monitoring in a damascene process Grant 6,716,650 - Langer , et al. April 6, 2	2004-04-06
Interface void monitoring in a damascene process App 20020168786 - Langer, Eckhard ; et al.	2002-11-14

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