Lan; James J. D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lan; James J. D..The latest application filed is for "ball grid array structure and method for packaging an integrated circuit chip".

Company Profile

0.10.0

Lan; James J. D. - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Ball grid array structure and method for packaging an integrated circuit chip Grant 6,034,427 - Lan , et al. March 7, 2	2000-03-07
Antifuse interconnect between two conducting layers of a printed circuit board Grant 5,962,815 - Lan , et al. October 5, 1	1999-10-05
Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect Grant 5,917,229 - Nathan , et al. June 29, 1	1999-06-29
Method and structure to interconnect traces of two conductive layers in a printed circuit board Grant 5,906,042 - Lan , et al. May 25, 1	1999-05-25
Multilayer board having insulating isolation rings Grant 5,872,338 - Lan , et al. February 16, 1	1999-02-16
Programmable cable and cable adapter using fuses and antifuses Grant 5,813,881 - Nathan , et al. September 29, 1	1998-09-29
Programmable/reprogramable structure using fuses and antifuses Grant 5,808,351 - Nathan , et al. September 15, 1	1998-09-15
Ball grid array structure and method for packaging an integrated circuit chip Grant 5,767,575 - Lan , et al. June 16, 1	1998-06-16
Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board Grant 5,572,409 - Nathan , et al. November 5, 1	1996-11-05
Method and structure for programming fuses Grant 5,537,108 - Nathan , et al. July 16, 1	1996-07-16

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