loadpatents
name:-0.011929988861084
name:-0.012350797653198
name:-0.00039291381835938
Lamorey; Mark Patent Filings

Lamorey; Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lamorey; Mark.The latest application filed is for "heterogeneous integration using wafer-to-wafer stacking with die size adjustment".

Company Profile
0.11.12
  • Lamorey; Mark - Williston VT
  • Lamorey; Mark - South Burlington VT US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
Grant 10,243,016 - Kumar , et al.
2019-03-26
Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
Grant 10,236,317 - Kumar , et al.
2019-03-19
Heterogeneous Integration Using Wafer-to-wafer Stacking With Die Size Adjustment
App 20180233526 - Kumar; Arvind ;   et al.
2018-08-16
Three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes
Grant 10,002,900 - Kumar , et al. June 19, 2
2018-06-19
Heterogeneous Integration Using Wafer-to-wafer Stacking With Die Size Adjustment
App 20180138228 - Kumar; Arvind ;   et al.
2018-05-17
Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
Grant 9,881,956 - Kumar , et al. January 30, 2
2018-01-30
Heterogeneous Integration Using Wafer-to-wafer Stacking With Die Size Adjustment
App 20170323920 - Kumar; Arvind ;   et al.
2017-11-09
Heterogeneous Integration Using Wafer-to-wafer Stacking With Die Size Adjustment
App 20170323919 - Kumar; Arvind ;   et al.
2017-11-09
Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits
Grant 8,653,662 - LaCroix , et al. February 18, 2
2014-02-18
Structure And Method For Monitoring Stress Induced Failures In Interlevel Dielectric Layers Of Solder Bump Integrated Circuits
App 20130292817 - LaCroix; Luke D. ;   et al.
2013-11-07
Optimized phase change write method
Grant 7,791,933 - Lamorey , et al. September 7, 2
2010-09-07
Sensing circuit for PCRAM applications
Grant 7,719,913 - Lung , et al. May 18, 2
2010-05-18
Novel Sensing Circuit For Pcram Applications
App 20100067285 - Lung; Hsiang-Lan ;   et al.
2010-03-18
Memory including two access devices per phase change element
Grant 7,652,914 - Nirschl , et al. January 26, 2
2010-01-26
Optimized phase change write method
Grant 7,626,860 - Lamorey , et al. December 1, 2
2009-12-01
Optimized Phase Change Write Method
App 20090161416 - Lamorey; Mark ;   et al.
2009-06-25
Phase change memory cell having a sidewall contact
Grant 7,541,609 - Nirschl , et al. June 2, 2
2009-06-02
Resistive Memory Including Bidirectional Write Operation
App 20090027943 - Nirschl; Thomas ;   et al.
2009-01-29
Optimized Phase Change Write Method
App 20080232158 - Lamorey; Mark ;   et al.
2008-09-25
Memory including two access devices per phase change element
App 20080165573 - Nirschl; Thomas ;   et al.
2008-07-10
Phase change memory cell having a sidewall contact
App 20080116442 - Nirschl; Thomas ;   et al.
2008-05-22

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