loadpatents
name:-0.11989998817444
name:-0.04232382774353
name:-0.0042409896850586
Lamb; Kirk D. Patent Filings

Lamb; Kirk D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lamb; Kirk D..The latest application filed is for "sizing a write cache buffer based on emergency data save parameters".

Company Profile
0.10.13
  • Lamb; Kirk D. - Poughkeepsie NY
  • Lamb; Kirk D. - Kingston NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Sizing a write cache buffer based on emergency data save parameters
Grant 10,007,611 - Lamb June 26, 2
2018-06-26
Sizing A Write Cache Buffer Based On Emergency Data Save Parameters
App 20170364443 - Lamb; Kirk D.
2017-12-21
Sizing a write cache buffer based on emergency data save parameters
Grant 9,767,030 - Lamb September 19, 2
2017-09-19
Sizing A Write Cache Buffer Based On Emergency Data Save Parameters
App 20160364336 - Lamb; Kirk D.
2016-12-15
Sizing a write cache buffer based on emergency data save parameters
Grant 9,436,612 - Lamb September 6, 2
2016-09-06
Sizing A Write Cache Buffer Based On Emergency Data Save Parameters
App 20160224445 - Lamb; Kirk D.
2016-08-04
Sizing A Write Cache Buffer Based On Emergency Data Save Parameters
App 20150317248 - Lamb; Kirk D.
2015-11-05
System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system
Grant 7,624,225 - Gower , et al. November 24, 2
2009-11-24
Method, System, And Computer Program Product For Mapping A Logical Design Onto An Integrated Circuit With Slack Apportionment
App 20080307374 - Gregerson; James C. ;   et al.
2008-12-11
System And Method For Providing Synchronous Dynamic Random Access Memory (sdram) Mode Register Shadowing In A Memory System
App 20080235444 - Gower; Kevin C. ;   et al.
2008-09-25
Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies
Grant 7,290,159 - Lamb , et al. October 30, 2
2007-10-30
System, method and storage medium for providing programmable delay chains for a memory system
App 20060164909 - Gower; Kevin C. ;   et al.
2006-07-27
Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies
App 20050268135 - Lamb, Kirk D. ;   et al.
2005-12-01
DDR-II driver impedance adjustment control algorithm and interface circuits
Grant 6,807,650 - Lamb , et al. October 19, 2
2004-10-19
Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test
Grant 6,757,857 - Lamb , et al. June 29, 2
2004-06-29
Digital temperature sensor (DTS) system to monitor temperature in a memory subsystem
Grant 6,662,136 - Lamb , et al. December 9, 2
2003-12-09
DDR-II driver impedance adjustment control algorithm and interface circuits
App 20030223303 - Lamb, Kirk D. ;   et al.
2003-12-04
Digital-to-analog Converter (dac) For Dynamic Adjustment Of Off-chip Driver Pull-up And Pull Down Impedance By Providing A Variable Reference Voltage To High Frequency Receiver And Driver Circuits For Commercial Memory
Grant 6,515,917 - Lamb , et al. February 4, 2
2003-02-04
Analog-to-digital Converter For Monitoring Vddq And Dynamically Updating Programmable Vref When Using High-frequency Receiver And Driver Circuits For Commercial Memory
App 20020149972 - Lamb, Kirk D. ;   et al.
2002-10-17
Digital-to-Analog Converter (DAC) for dynamic adjustment of off-chip driver pull-up and pull down impedance by providing a variable reference voltage to high frequency receiver and driver circuits for commercial memory
App 20020145919 - Lamb, Kirk D. ;   et al.
2002-10-10
Digital temperature sensor (DTS) system to monitor temperature in a memory subsystem
App 20020147564 - Lamb, Kirk D. ;   et al.
2002-10-10
Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test
App 20020147949 - Lamb, Kirk D. ;   et al.
2002-10-10
Time-division-multiplexed data transmission system
Grant 5,282,210 - Slegel , et al. January 25, 1
1994-01-25

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