Lamant; Gilles S. C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lamant; Gilles S. C..The latest application filed is for "method and system for implementing stacked vias".

Company Profile

1.24.8

Lamant; Gilles S. C. - Sunnyvale CA
Lamant; Gilles S.C. - Lamant CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and systems for centering of pins during instance abutment Grant 10,235,490 - Mallon , et al.	2019-03-19
Methods and systems for customizable editing of completed chain of abutted instances Grant 9,690,893 - Ferguson , et al. June 27, 2	2017-06-27
Method for representing a photonic waveguide port and port specification Grant 9,684,761 - Lamant June 20, 2	2017-06-20
Method and system for automatically establishing a component description format (CDF) debugging environment Grant 9,336,123 - Lamant , et al. May 10, 2	2016-05-10
Automated adjustment of wire connections in computer-assisted design of circuits Grant 9,208,277 - Lamant December 8, 2	2015-12-08
Method and system for implementing an improved interface for designing electronic layouts Grant 9,053,289 - Lamant , et al. June 9, 2	2015-06-09
Method and system for automatically establishing a component description format (CDF) debugging environment Grant 8,726,209 - Lamant , et al. May 13, 2	2014-05-13
Annotation management for hierarchical designs of integrated circuits Grant 8,533,650 - Arsintescu , et al. September 10, 2	2013-09-10
Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processes Grant 8,516,404 - Cao , et al. August 20, 2	2013-08-20
Spine selection mode for layout editing Grant 8,402,417 - Lamant March 19, 2	2013-03-19
Method and system for implementing multiuser cached parameterized cells Grant 8,364,656 - Arora , et al. January 29, 2	2013-01-29
Method And System For Implementing Stacked Vias App 20120030644 - Lamant; Gilles S. C.	2012-02-02
Method and system for implementing stacked vias Grant 8,042,088 - Lamant October 18, 2	2011-10-18
Method and system for implementing cached parameterized cells Grant 7,971,175 - Ginetti , et al. June 28, 2	2011-06-28
Method and system for implementing abstract layout structures with parameterized cells Grant 7,949,987 - Ginetti , et al. May 24, 2	2011-05-24
Registry for electronic design automation of integrated circuits Grant 7,945,890 - Colwell , et al. May 17, 2	2011-05-17
Spine Selection Mode For Layout Editing App 20110099530 - Lamant; Gilles S.C.	2011-04-28
Annotation Management For Hierarchical Designs Of Integrated Circuits App 20110066995 - Arsintescu; Bogdan G. ; et al.	2011-03-17
Spine selection mode for layout editing Grant 7,861,205 - Lamant December 28, 2	2010-12-28
Methods and systems for physical hierarchy configuration engine and graphical editor Grant 7,805,698 - Ferguson , et al. September 28, 2	2010-09-28
Method And System For Implementing Multiuser Cached Parameterized Cells App 20100115207 - ARORA; Rajan ; et al.	2010-05-06
Spine Selection Mode For Layout Editing App 20100004902 - LAMANT; Gilles S. C.	2010-01-07
Method and System for Implementing Stacked Vias App 20090172624 - Lamant; Gilles S.C.	2009-07-02
Registry For Electronic Design Automation Of Integrated Circuits App 20090113369 - Colwell; Regis ; et al.	2009-04-30
Method And System For Implementing Cached Parameterized Cells App 20090007031 - Ginetti; Arnold ; et al.	2009-01-01

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