Lam; Chung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lam; Chung.The latest application filed is for "encryption engine with an undetectable/tamper-proof private key in late node cmos technology".

Company Profile

5.20.10

Lam; Chung - Peekskill NY
Lam; Chung - Redwood City CA
Lam; Chung - Williston VT
Lam; Chung - Redwood Shores CA
LAM, CHUNG - FREMONT CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology Grant 11,216,595 - Boivie , et al. January 4, 2	2022-01-04
Encryption engine with an undetectable/tamper proof private key in late node CMOS technology Grant 10,997,321 - Boivie , et al. May 4, 2	2021-05-04
Stackable cross-point phase-change material memory array with a resistive liner Grant 10,763,307 - Carta , et al. Sep	2020-09-01
Encryption Engine With An Undetectable/tamper-proof Private Key In Late Node Cmos Technology App 20200019732 - Boivie; Richard H. ; et al.	2020-01-16
Encryption Engine With An Undetectable/tamper-proof Private Key In Late Node Cmos Technology App 20200019731 - Boivie; Richard H. ; et al.	2020-01-16
Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology Grant 10,423,805 - Boivie , et al. Sept	2019-09-24
Encryption Engine With An Undetectable/tamper-proof Private Key In Late Node Cmos Technology App 20180181774 - Boivie; Richard H. ; et al.	2018-06-28
Phase Change Memory With Dual Word Lines and Source Lines and Method of Operating Same App 20100195378 - Lung; Hsiang Lan ; et al.	2010-08-05
Phase Change Memory With Dual Word Lines And Source Lines And Method Of Operating Same App 20090034323 - Lung; Hsiang Lan ; et al.	2009-02-05
Buffering and interleaving data transfer between a chipset and memory modules Grant 7,249,232 - Halbert , et al. July 24, 2	2007-07-24
Methods and systems for performing horological functions using time cells Grant 7,173,882 - Berstis , et al. February 6, 2	2007-02-06
Dual-port buffer-to-memory interface Grant 7,024,518 - Halbert , et al. April 4, 2	2006-04-04
Methods and systems for performing horological functions using time cells App 20050185515 - Berstis, Viktors ; et al.	2005-08-25
Batteryless, oscillatorless, binary time cell usable as an horological device with associated programming methods and devices Grant 6,856,581 - Berstis , et al. February 15, 2	2005-02-15
Batteryless, osciliatorless, analog time cell usable as an horological device with associated programming methods and devices Grant 6,831,879 - Berstis , et al. December 14, 2	2004-12-14
Sensing methods and devices for a batteryless, oscillatorless, binary time cell usable as an horological device Grant 6,829,200 - Berstis , et al. December 7, 2	2004-12-07
Sensing methods and devices for a batteryless, oscillatorless, analog time cell usable as an horological device Grant 6,826,128 - Berstis , et al. November 30, 2	2004-11-30
Buffering data transfer between a chipset and memory modules Grant 6,820,163 - McCall , et al. November 16, 2	2004-11-16
Buffering and interleaving data transfer between a chipset and memory modules App 20040188704 - Halbert, John B. ; et al.	2004-09-30
Dual-port buffer-to-memory interface Grant 6,742,098 - Halbert , et al. May 25, 2	2004-05-25
Buffering and interleaving data transfer between a chipset and memory modules Grant 6,697,888 - Halbert , et al. February 24, 2	2004-02-24
Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing Grant 6,625,687 - Halbert , et al. September 23, 2	2003-09-23
Buffer to multiply memory interface Grant 6,553,450 - Dodd , et al. April 22, 2	2003-04-22
Multi-tier point-to-point buffered memory interface Grant 6,493,250 - Halbert , et al. December 10, 2	2002-12-10
Board Level Decapsulator App 20020144975 - LAM, CHUNG	2002-10-10
Dual-port buffer-to-memory interface App 20020112119 - Halbert, John B. ; et al.	2002-08-15
Multi-tier Point-to-point Buffered Memory Interface App 20020084458 - Halbert, John B. ; et al.	2002-07-04
Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules Grant 6,317,352 - Halbert , et al. November 13, 2	2001-11-13
Board Level Decapsulator Grant 5,932,061 - Lam August 3, 1	1999-08-03
Test generator system for controllably inducing power pin latch-up and signal pin latch-up in a CMOS device Grant 5,541,547 - Lam July 30, 1	1996-07-30

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