Lakshmanan; Viswanathan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lakshmanan; Viswanathan.The latest application filed is for "waiver mechanism for physical verification of system designs".

Company Profile

0.17.13

Lakshmanan; Viswanathan - Thornton CO
Lakshmanan; Viswanathan - Thorton CO
Lakshmanan; Viswanathan - Westminster CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Waiver mechanism for physical verification of system designs Grant 8,046,726 - Lakshmanan , et al. October 25, 2	2011-10-25
Unified layer stack architecture Grant 7,853,901 - Lakshmanan , et al. December 14, 2	2010-12-14
N cell height decoupling circuit Grant 7,829,973 - Schultz , et al. November 9, 2	2010-11-09
Waiver Mechanism For Physical Verification Of System Designs App 20100070936 - Lakshmanan; Viswanathan ; et al.	2010-03-18
Unified Layer Stack Architecture App 20090271755 - Lakshmanan; Viswanathan ; et al.	2009-10-29
N Cell Height Decoupling Circuit App 20090051006 - Schultz; Richard T. ; et al.	2009-02-26
Method and system for layout versus schematic validation of integrated circuit designs Grant 7,480,878 - Holesovsky , et al. January 20, 2	2009-01-20
Method of automating place and route corrections for an integrated circuit design from physical design validation Grant 7,302,654 - Lakshmanan , et al. November 27, 2	2007-11-27
Incremental dummy metal insertions Grant 7,260,803 - Lakshmanan , et al. August 21, 2	2007-08-21
Method and computer program product for trimming the analysis of physical layout versus schematic design comparison App 20070157140 - Holesovsky; Alan Lee ; et al.	2007-07-05
Method of implementing an engineering change order in an integrated circuit design by windows Grant 7,231,626 - Hoff , et al. June 12, 2	2007-06-12
Method and computer program for verifying an incremental change to an integrated circuit design Grant 7,219,317 - Lakshmanan , et al. May 15, 2	2007-05-15
Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design Grant 7,149,989 - Lakshmanan , et al. December 12, 2	2006-12-12
Method of partitioning an integrated circuit design for physical design verification Grant 7,107,559 - Lakshmanan , et al. September 12, 2	2006-09-12
Method of implementing an engineering change order in an integrated circuit design by windows App 20060136855 - Hoff; Jason K. ; et al.	2006-06-22
Web based OLA memory generator Grant 7,051,318 - Lakshmanan , et al. May 23, 2	2006-05-23
Method of automating place and route corrections for an integrated circuit design from physical design validation App 20060095883 - Lakshmanan; Viswanathan ; et al.	2006-05-04
Method of automating place and route corrections for an integrated circuit design from physical design validation App 20060090144 - Lakshmanan; Viswanathan ; et al.	2006-04-27
Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design App 20060064656 - Lakshmanan; Viswanathan ; et al.	2006-03-23
Method and apparatus for implementing engineering change orders Grant 7,007,248 - Blinne , et al. February 28, 2	2006-02-28
Method and computer program for verifying an incremental change to an integrated circuit design App 20050235234 - Lakshmanan, Viswanathan ; et al.	2005-10-20
Method of partitioning an integrated circuit design for physical design verification App 20050097488 - Lakshmanan, Viswanathan ; et al.	2005-05-05
Incremental dummy metal insertions App 20050080607 - Lakshmanan, Viswanathan ; et al.	2005-04-14
Method and apparatus for implementing engineering change orders App 20040230920 - Blinne, Richard ; et al.	2004-11-18
Chip design method for designing integrated circuit chips with embedded memories Grant 6,775,811 - Lakshmanan , et al. August 10, 2	2004-08-10
Method to debug IKOS method Grant 6,691,288 - Fakhry , et al. February 10, 2	2004-02-10
Verilog to vital translator Grant 6,668,359 - Fakhry , et al. December 23, 2	2003-12-23
Method to translate UDPs using gate primitives Grant 6,658,630 - Threatt , et al. December 2, 2	2003-12-02
Chip design method for designing integrated circuit chips with embedded memories App 20030221177 - Lakshmanan, Viswanathan ; et al.	2003-11-27
Generating standard delay format files with conditional path delay for designing integrated circuits Grant 6,453,451 - Lakshmanan , et al. September 17, 2	2002-09-17

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