Lakhani; Vinod C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lakhani; Vinod C..The latest application filed is for "method for assigning addresses to memory devices".

Company Profile

0.33.16

Lakhani; Vinod C. - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for assigning addresses to memory devices Grant 9,552,311 - Norman , et al. January 24, 2	2017-01-24
Method For Assigning Addresses To Memory Devices App 20140281178 - Norman; Robert D. ; et al.	2014-09-18
Method for assigning addresses to memory devices Grant 8,745,355 - Norman , et al. June 3, 2	2014-06-03
Method For Assigning Addresses To Memory Devices App 20090089536 - Norman; Robert D. ; et al.	2009-04-02
Method for assigning addresses to memory devices Grant 7,444,458 - Norman , et al. October 28, 2	2008-10-28
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 7,251,187 - Lakhani , et al. July 31, 2	2007-07-31
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 7,133,323 - Lakhani , et al. November 7, 2	2006-11-07
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 7,130,239 - Lakhani , et al. October 31, 2	2006-10-31
Memory system, method and predeconding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20050281120 - Lakhani, Vinod C. ; et al.	2005-12-22
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20050281121 - Lakhani, Vinod C. ; et al.	2005-12-22
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20050281122 - Lakhani, Vinod C. ; et al.	2005-12-22
System and method for assigning addresses to memory devices Grant 6,965,923 - Norman , et al. November 15, 2	2005-11-15
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure Grant 6,961,805 - Lakhani , et al. November 1, 2	2005-11-01
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 6,954,400 - Lakhani , et al. October 11, 2	2005-10-11
Segmented non-volatile memory array with multiple sources having improved source line decode circuitry App 20050190638 - Chevallier, Christophe J. ; et al.	2005-09-01
Memory System And Method For Assigning Addresses To Memory Devices App 20050160216 - Norman, Robert D. ; et al.	2005-07-21
Segmented non-volatile memory array with multiple sources having improved source line decode circuitry Grant 6,914,813 - Chevallier , et al. July 5, 2	2005-07-05
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 6,856,571 - Lakhani , et al. February 15, 2	2005-02-15
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20050002264 - Lakhani, Vinod C. ; et al.	2005-01-06
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 6,809,987 - Lakhani , et al. October 26, 2	2004-10-26
Segmented non-volatile memory array with multiple sources having improved source line decode circuitry Grant 6,760,267 - Chevallier , et al. July 6, 2	2004-07-06
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20030126384 - Lakhani, Vinod C. ; et al.	2003-07-03
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20030126386 - Lakhani, Vinod C. ; et al.	2003-07-03
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20030126385 - Lakhani, Vinod C. ; et al.	2003-07-03
Memory system having flexible bus structure and method Grant 6,567,335 - Norman , et al. May 20, 2	2003-05-20
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 6,507,885 - Lakhani , et al. January 14, 2	2003-01-14
Segmented non-volatile memory array with multiple sources having improved source line decode circuitry App 20020196696 - Chevallier, Christophe J. ; et al.	2002-12-26
Segmented non-volatile memory array with multiple sources having improved source line decode circuitry App 20020191474 - Chevallier, Christophe J. ; et al.	2002-12-19
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure App 20020099903 - Lakhani, Vinod C. ; et al.	2002-07-25
Memory system having flexible architecture and method Grant 6,363,454 - Lakhani , et al. March 26, 2	2002-03-26
Memory system having flexible bus structure and method Grant 6,353,571 - Norman , et al. March 5, 2	2002-03-05
Memory system having flexible addressing and method App 20020002653 - Lakhani, Vinod C. ; et al.	2002-01-03
Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit Grant 6,307,425 - Chevallier , et al. October 23, 2	2001-10-23
Memory system having flexible addressing and method using tag and data bus communication Grant 6,253,277 - Lakhani , et al. June 26, 2	2001-06-26
Memory system having serial selection of memory devices and method App 20010003837 - Norman, Robert D. ; et al.	2001-06-14
Memory system having flexible bus structure and method Grant 6,212,123 - Norman , et al. April 3, 2	2001-04-03
System and method for assigning addresses to memory devices Grant 6,175,891 - Norman , et al. January 16, 2	2001-01-16
Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit Grant 6,154,088 - Chevallier , et al. November 28, 2	2000-11-28
Memory system having flexible addressing and method using tag and data bus communication Grant 6,078,985 - Lakhani , et al. June 20, 2	2000-06-20
Memory system having flexible architecture and method Grant 6,073,204 - Lakhani , et al. June 6, 2	2000-06-06
Apparatus and method for selecting data bits read from a multistate memory Grant 6,052,303 - Chevallier , et al. April 18, 2	2000-04-18
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Grant 6,047,352 - Lakhani , et al. April 4, 2	2000-04-04
Memory system having flexible bus structure and method Grant 6,021,459 - Norman , et al. February 1, 2	2000-02-01
Memory system having read modify write function and method Grant 5,974,499 - Norman , et al. October 26, 1	1999-10-26
System and method for selecting shorted wordlines of an array having dual wordline drivers Grant 5,898,637 - Lakhani , et al. April 27, 1	1999-04-27
Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit Grant 5,818,289 - Chevallier , et al. October 6, 1	1998-10-06
Segmented non-volatile memory array with multiple sources having improved source line decode circuitry Grant 5,687,117 - Chevallier , et al. November 11, 1	1997-11-11
Segmented non-volatile memory array with multiple sources with improved word line control circuitry Grant 5,673,224 - Chevallier , et al. September 30, 1	1997-09-30

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