Lai; Tin H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lai; Tin H..The latest application filed is for "clock and data recovery circuitry with auto-speed negotiation and other possible features".

Company Profile

0.23.9

Lai; Tin H. - San Jose CA
Lai; Tin H - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Clock and data recovery circuitry with auto-speed negotiation and other possible features Grant 8,829,958 - Asaduzzaman , et al. September 9, 2	2014-09-09
Clock and data recovery circuitry with auto-speed negotiation and other possible features Grant 8,811,555 - Asaduzzaman , et al. August 19, 2	2014-08-19
Clock And Data Recovery Circuitry With Auto-speed Negotiation And Other Possible Features App 20130093482 - Asaduzzaman; Kazi ; et al.	2013-04-18
Techniques for decision feedback equalization that reduce variations in the tap weight Grant 8,416,898 - Luo , et al. April 9, 2	2013-04-09
Digital adaptation circuitry and methods for programmable logic devices Grant 8,208,523 - Wong , et al. June 26, 2	2012-06-26
Programmable adaptation convergence detection Grant 8,208,528 - Lai , et al. June 26, 2	2012-06-26
Adaptive equalization using data level detection Grant 8,175,143 - Wong , et al. May 8, 2	2012-05-08
Method and apparatus for standby voltage offset cancellation Grant 8,098,087 - Lam , et al. January 17, 2	2012-01-17
Equalization circuitry including a digital-to-analog converter having a voltage divider and a multiplexer Grant 8,063,807 - Lai , et al. November 22, 2	2011-11-22
Clock And Data Recovery Circuitry With Auto-speed Negotiation And Other Possible Features App 20110188621 - Asaduzzaman; Kazi ; et al.	2011-08-04
Digital Adaptation Circuitry And Methods For Programmable Logic Devices App 20110188564 - Wong; Wilson ; et al.	2011-08-04
Digital adaptation circuitry and methods for programmable logic devices Grant 7,920,621 - Wong , et al. April 5, 2	2011-04-05
Signal offset cancellation Grant 7,898,313 - Lai , et al. March 1, 2	2011-03-01
Half-rate DFE with duplicate path for high data-rate operation Grant 7,782,935 - Wong , et al. August 24, 2	2010-08-24
Programmable digital equalization control circuitry and methods Grant 7,760,799 - Lai , et al. July 20, 2	2010-07-20
Signal adjustment receiver circuitry Grant 7,733,982 - Wong , et al. June 8, 2	2010-06-08
Signal adjustment receiver circuitry Grant 7,733,997 - Lai , et al. June 8, 2	2010-06-08
Signal offset cancellation Grant 7,710,180 - Lai , et al. May 4, 2	2010-05-04
Signal Adjustment Receiver Circuitry App 20090284292 - Wong; Wilson ; et al.	2009-11-19
Signal Adjustment Receiver Circuitry App 20090285275 - Wong; Wilson ; et al.	2009-11-19
Signal adjustment receiver circuitry Grant 7,590,174 - Wong , et al. September 15, 2	2009-09-15
Comparator offset cancellation assisted by PLD resources Grant 7,541,857 - Wong , et al. June 2, 2	2009-06-02
H-tree driver circuitry Grant 7,514,968 - Lai , et al. April 7, 2	2009-04-07
Signal offset cancellation Grant 7,368,968 - Lai , et al. May 6, 2	2008-05-06
Dynamic bias circuit Grant 7,358,883 - Lai , et al. April 15, 2	2008-04-15
Digital adaptation circuitry and methods for programmable logic devices App 20080069276 - Wong; Wilson ; et al.	2008-03-20
Resistance compensated DAC ladder Grant 7,336,211 - Lai , et al. February 26, 2	2008-02-26
Signal adjustment receiver circuitry App 20070147478 - Lai; Tin H. ; et al.	2007-06-28
Signal adjustment receiver circuitry App 20070140387 - Wong; Wilson ; et al.	2007-06-21
Programmable digital equalization control circuitry and methods App 20070071084 - Lai; Tin H. ; et al.	2007-03-29

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