Lai; Jiun Ren

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lai; Jiun Ren.The latest application filed is for "3dic architecture with interposer or bonding dies".

Company Profile

4.8.10

Lai; Jiun Ren - Zhubei City TW
Lai; Jiun Ren - Zhubei TW
Lai; Jiun-Ren - Pingtung TW
Lai, Jiun-Ren - Hsinchu TW
Lai, Jiun-Ren - Pingtung City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
3DIC Architecture with Interposer or Bonding Dies App 20210167018 - Hu; Hsien-Pin ; et al.	2021-06-03
Method for forming a 3D IC architecture including forming a first die on a first side of a first interconnect structure and a second die in an opening formed in a second side Grant 10,923,431 - Hu , et al. February 16, 2	2021-02-16
3DIC Architecture with Interposer for Bonding Dies App 20190273046 - Hu; Hsien-Pin ; et al.	2019-09-05
3D IC architecture with interposer and interconnect structure for bonding dies Grant 10,297,550 - Hu , et al.	2019-05-21
3DIC Architecture with Interposer for Bonding Dies App 20110193221 - Hu; Hsien-Pin ; et al.	2011-08-11
3DIC Architecture with Die Inside Interposer App 20110193235 - Hu; Hsien-Pin ; et al.	2011-08-11
Method of improving device resistance Grant 6,849,526 - Lai , et al. February 1, 2	2005-02-01
Methods for reducing cell pitch in semiconductor devices App 20050020043 - Lai, Jiun-Ren	2005-01-27
Method for forming an electrical insulating layer on bit lines of the flash memory Grant 6,787,408 - Chen , et al. September 7, 2	2004-09-07
[structure Of A Memory Device And Fabrication Method Thereof] App 20040161896 - Lai, Jiun-Ren ; et al.	2004-08-19
Pitch reduction in semiconductor fabrication Grant 6,734,107 - Lai , et al. May 11, 2	2004-05-11
Structure of a memory device with buried bit line Grant 6,720,629 - Lai , et al. April 13, 2	2004-04-13
Structure Of A Memory Device And Fabrication Method Thereof App 20040004256 - Lai, Jiun-Ren ; et al.	2004-01-08
Pitch reduction in semiconductor fabrication App 20030232474 - Lai, Jiun-Ren ; et al.	2003-12-18
Method for reducing pitch between conductive features, and structure formed using the method Grant 6,548,385 - Lai April 15, 2	2003-04-15
Method for forming an electrical insulating layer on bit lines of the flash memory App 20020175139 - Chen, Chien-Wei ; et al.	2002-11-28
Method for fabricating electrically insulating layers App 20020132484 - Lai, Jiun-Ren ; et al.	2002-09-19

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