| Patent | Date |
|---|
Dislocation engineering using a scanned laser
Grant 8,865,571 - Lai , et al. October 21, 2 | 2014-10-21 |
Dislocation engineering using a scanned laser
Grant 8,865,572 - Lai , et al. October 21, 2 | 2014-10-21 |
Dislocation Engineering Using A Scanned Laser
App 20140154872 - Lai; Chung Woh ; et al. | 2014-06-05 |
Dislocation Engineering Using A Scanned Laser
App 20140154873 - Lai; Chung Woh ; et al. | 2014-06-05 |
Capacitor top plate over source/drain to form a 1T memory device
Grant 8,716,081 - Teo , et al. May 6, 2 | 2014-05-06 |
Spacer-less low-K dielectric processes
Grant 8,624,329 - Lee , et al. January 7, 2 | 2014-01-07 |
Dislocation Engineering Using a Scanned Laser
App 20120294322 - Lai; Chung Woh ; et al. | 2012-11-22 |
Hybrid orientation substrate with stress layer
Grant 8,274,115 - Teo , et al. September 25, 2 | 2012-09-25 |
Methods of forming p-channel field effect transistors having SiGe source/drain regions
Grant 8,198,194 - Yang , et al. June 12, 2 | 2012-06-12 |
Dislocation Engineering Using a Scanned Laser
App 20120138823 - Lai; Chung Woh ; et al. | 2012-06-07 |
Method of forming shallow trench isolation structures for integrated circuits
Grant 8,178,417 - Mishra , et al. May 15, 2 | 2012-05-15 |
Nested and isolated transistors with reduced impedance difference
Grant 8,143,651 - Widodo , et al. March 27, 2 | 2012-03-27 |
Dislocation engineering using a scanned laser
Grant 8,138,066 - Lai , et al. March 20, 2 | 2012-03-20 |
Method of manufacture of an integrated circuit system with self-aligned isolation structures
Grant 8,053,327 - Mishra , et al. November 8, 2 | 2011-11-08 |
Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions
App 20110237039 - Yang; Jong-Ho ; et al. | 2011-09-29 |
Memory cell structure and method for fabrication thereof
Grant 7,999,300 - Lun , et al. August 16, 2 | 2011-08-16 |
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
Grant 7,999,325 - Teh , et al. August 16, 2 | 2011-08-16 |
Method and apparatus for post silicide spacer removal
Grant 7,977,185 - Greene , et al. July 12, 2 | 2011-07-12 |
Semiconductor fabrication process including an SiGe rework method
Grant 7,955,936 - Tan , et al. June 7, 2 | 2011-06-07 |
Stress optimization in dual embedded epitaxially grown semiconductor processing
Grant 7,935,593 - Yang , et al. May 3, 2 | 2011-05-03 |
Integrated circuit having a plurality of MOSFET devices
Grant 7,932,178 - Teo , et al. April 26, 2 | 2011-04-26 |
Nested And Isolated Transistors With Reduced Impedance Difference
App 20100301424 - WIDODO; Johnny ; et al. | 2010-12-02 |
Methods of manufacturing semiconductor devices and structures thereof
Grant 7,838,372 - Han , et al. November 23, 2 | 2010-11-23 |
Integrated circuit system employing selective epitaxial growth technology
Grant 7,795,680 - Liu , et al. September 14, 2 | 2010-09-14 |
Stress Optimization In Dual Embedded Epitaxially Grown Semiconductor Processing
App 20100197093 - Yang; Jong Ho ; et al. | 2010-08-05 |
Nested and isolated transistors with reduced impedance difference
Grant 7,767,577 - Widodo , et al. August 3, 2 | 2010-08-03 |
Memory Cell Structure And Method For Fabrication Thereof
App 20100187587 - LUN; Zhao ; et al. | 2010-07-29 |
Dislocation Engineering Using A Scanned Laser
App 20100081259 - Lai; Chung Woh ; et al. | 2010-04-01 |
Spacer-less Low-K Dielectric Processes
App 20100059831 - Lee; Yong Meng ; et al. | 2010-03-11 |
Integrated Circuit System Employing Single Mask Layer Technique For Well Formation
App 20100009527 - Lee; Yong Meng ; et al. | 2010-01-14 |
Semiconductor Fabrication Process Including An SiGe Rework Method
App 20100009502 - Tan; Yong Siang ; et al. | 2010-01-14 |
Methods of Manufacturing Semiconductor Devices and Structures Thereof
App 20090289379 - Han; Jin-Ping ; et al. | 2009-11-26 |
Spacer-less low-k dielectric processes
Grant 7,615,427 - Lee , et al. November 10, 2 | 2009-11-10 |
Method Of Forming Shallow Trench Isolation Structures For Integrated Circuits
App 20090261448 - MISHRA; Shailendra ; et al. | 2009-10-22 |
Hybrid Orientation Substrate With Stress Layer
App 20090236663 - Teo; Lee Wee ; et al. | 2009-09-24 |
Nested And Isolated Transistors With Reduced Impedance Difference
App 20090206408 - WIDODO; Johnny ; et al. | 2009-08-20 |
Integrated Circuit System Employing Selective Epitaxial Growth Technology
App 20090146262 - Liu; Huang ; et al. | 2009-06-11 |
Integrated Circuit System Employing Diffused Source/drain Extensions
App 20090146181 - Lai; Chung Woh ; et al. | 2009-06-11 |
Strained Semiconductor Device and Method of Making Same
App 20090050972 - Lindsay; Richard ; et al. | 2009-02-26 |
Method To Remove Spacer After Salicidation To Enhance Contact Etch Stop Liner Stress On Mos
App 20090026549 - TEH; Young Way ; et al. | 2009-01-29 |
Semiconductor System Having Complementary Strained Channels
App 20080315317 - Lai; Chung Woh ; et al. | 2008-12-25 |
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
Grant 7,445,978 - Teh , et al. November 4, 2 | 2008-11-04 |
Capacitor Top Plate Over Source/drain To Form A 1t Memory Device
App 20080224228 - Teo; Lee Wee ; et al. | 2008-09-18 |
Integrated Circuit Having A Plurality Of Mosfet Devices
App 20080157223 - Teo; Lee Wee ; et al. | 2008-07-03 |
Integrated Circuit System With Isolation
App 20080150074 - Mishra; Shailendra ; et al. | 2008-06-26 |
Spacer-less low-k dielectric processes
App 20070281410 - Lee; Yong Meng ; et al. | 2007-12-06 |
Composite stress spacer
Grant 7,256,084 - Lim , et al. August 14, 2 | 2007-08-14 |
Method And Apparatus For Post Silicide Spacer Removal
App 20070161244 - Greene; Brian J. ; et al. | 2007-07-12 |
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
App 20060249794 - Teh; Young Way ; et al. | 2006-11-09 |
Composite stress spacer
App 20060252194 - Lim; Khee Yong ; et al. | 2006-11-09 |
Method of cobalt silicidation using an oxide-Titanium interlayer
Grant 6,653,227 - Lai , et al. November 25, 2 | 2003-11-25 |
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