loadpatents
name:-0.020832061767578
name:-0.016829013824463
name:-0.0037188529968262
Lahnor; Peter Patent Filings

Lahnor; Peter

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lahnor; Peter.The latest application filed is for "solar module, solar module-integrable assembly and power generation system".

Company Profile
1.11.15
  • Lahnor; Peter - Habichtswald DE
  • Lahnor; Peter - Kassel DE
  • Lahnor; Peter - Dresden DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Solar Module, Solar Module-integrable Assembly And Power Generation System
App 20220090826 - Thiel; Raimund ;   et al.
2022-03-24
Unfolding bridge, inverter having reactive-power capability, and polarity reversing method
Grant 10,530,273 - Friebe , et al. J
2020-01-07
Unfolding Bridge, Inverter Having Reactive-power Capability, And Polarity Reversing Method
App 20180152118 - Friebe; Jens ;   et al.
2018-05-31
Interconnect structure for semiconductor devices
Grant 8,138,538 - Moll , et al. March 20, 2
2012-03-20
Method and apparatus for reducing charge trapping in high-k dielectric material
Grant 7,894,240 - Beck , et al. February 22, 2
2011-02-22
Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes
Grant 7,776,759 - Lahnor , et al. August 17, 2
2010-08-17
Method for Structuring a Layered Stack
App 20100099253 - Baier; Ulrich ;   et al.
2010-04-22
Interconnect Structure For Semiconductor Devices
App 20100090264 - Moll; Hans-Peter ;   et al.
2010-04-15
Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material
App 20100054022 - Beck; Michael ;   et al.
2010-03-04
Apparatus And Method Of Manufacturing An Integrated Circuit
App 20090142916 - Prenz; Heike ;   et al.
2009-06-04
Integrated Circuit Having A Memory
App 20080217672 - Popp; Martin ;   et al.
2008-09-11
Methods For Forming An Integrated Circuit, Including Openings In A Mold Layer
App 20070286945 - Lahnor; Peter ;   et al.
2007-12-13
Method of determining the endpoint of a planarization process
Grant 6,932,674 - Lahnor , et al. August 23, 2
2005-08-23
Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices
Grant 6,893,968 - Lahnor , et al. May 17, 2
2005-05-17
Method of planarizing substrates
Grant 6,827,635 - Lahnor , et al. December 7, 2
2004-12-07
CMP process
Grant 6,821,894 - Lahnor , et al. November 23, 2
2004-11-23
Method Of Planarizing Substrates
App 20040185756 - Lahnor, Peter ;   et al.
2004-09-23
Method Of Determining The Endpoint Of A Planarization Process
App 20040176015 - Lahnor, Peter ;   et al.
2004-09-09
Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers
Grant 6,787,431 - Lahnor September 7, 2
2004-09-07
Semiconductor substrate holder for chemical-mechanical polishing containing a movable plate
Grant 6,695,687 - Hollatz , et al. February 24, 2
2004-02-24
Method of simultaneously polishing a plurality of objects of a similar type, in particular silicon wafers, on a polishing installation
Grant 6,689,691 - Lahnor February 10, 2
2004-02-10
Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices
App 20030190809 - Lahnor, Peter ;   et al.
2003-10-09
Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers
App 20030096488 - Lahnor, Peter
2003-05-22
Semiconductor substrate holder for chemical-mechanical polishing containing a movable plate
App 20020177394 - Hollatz, Mark ;   et al.
2002-11-28
Method of simultaneously polishing a plurality of objects of a similar type, in particular silicon wafers, on a polishing installation
App 20020146877 - Lahnor, Peter
2002-10-10
CMP process
App 20020036181 - Lahnor, Peter ;   et al.
2002-03-28

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