Lahner; Juergen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lahner; Juergen.The latest application filed is for "enhanced method of optimizing multiplex structures and multiplex control structures in rtl code".

Company Profile

0.12.8

Lahner; Juergen - Morgan Hill CA
Lahner; Juergen - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code Grant 7,594,201 - Lahner , et al. September 22, 2	2009-09-22
Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design Grant 7,412,678 - Lahner , et al. August 12, 2	2008-08-12
Method of associating timing violations with critical structures in an integrated circuit design Grant 7,380,228 - Fry , et al. May 27, 2	2008-05-27
Enhanced Method Of Optimizing Multiplex Structures And Multiplex Control Structures In Rtl Code App 20060282801 - Lahner; Juergen ; et al.	2006-12-14
Method of optimizing RTL code for multiplex structures Grant 7,086,015 - Lahner , et al. August 1, 2	2006-08-01
Automated analysis of RTL code containing ASIC vendor rules Grant 7,082,584 - Lahner , et al. July 25, 2	2006-07-25
Method of associating timing violations with critical structures in an integrated circuit design App 20060101363 - Fry; Randall P. ; et al.	2006-05-11
Advanced design format library for integrated circuit design synthesis and floorplanning tools Grant 6,990,651 - Balasubramanian , et al. January 24, 2	2006-01-24
Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design App 20050273741 - Lahner, Juergen ; et al.	2005-12-08
Method of optimizing RTL code for multiplex structures App 20050257180 - Lahner, Juergen ; et al.	2005-11-17
Congestion estimation for register transfer level code Grant 6,907,588 - Balasubramanian , et al. June 14, 2	2005-06-14
Advanced design format library for integrated circuit design synthesis and floorplanning tools App 20040230919 - Balasubramanian, Balamurugan ; et al.	2004-11-18
Automated analysis of RTL code containing ASIC vendor rules App 20040221249 - Lahner, Juergen ; et al.	2004-11-04
Buffer cell insertion and electronic design automation Grant 6,766,499 - Mbouombouo , et al. July 20, 2	2004-07-20
Congestion estimation for register transfer level code App 20040128639 - Balasubramanian, Balamurugan ; et al.	2004-07-01
Length Matrix Generator For Register Transfer Level Code App 20040128640 - Adusumalli, Srinivas ; et al.	2004-07-01
Length matrix generator for register transfer level code Grant 6,757,885 - Adusumalli , et al. June 29, 2	2004-06-29
Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak power Grant 6,546,538 - Rubdi , et al. April 8, 2	2003-04-08
Cell interconnect delay library for integrated circuit design Grant 6,532,576 - Mbouombouo , et al. March 11, 2	2003-03-11
RTL code optimization for resource sharing structures Grant 6,438,730 - Atmakuri , et al. August 20, 2	2002-08-20

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