LAGRASTA; Sebastien

Patent Applications and Registrations

Patent applications and USPTO patent grants for LAGRASTA; Sebastien.The latest application filed is for "electronic component manufacturing method".

Company Profile

3.6.8

LAGRASTA; Sebastien - La Terrasse FR
Lagrasta; Sebastien - Montbonnot Saint Martin FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electronic Component Manufacturing Method App 20220020924 - CANVEL; Yann ; et al.	2022-01-20
Electronic component manufacturing method Grant 11,152,570 - Canvel , et al. October 19, 2	2021-10-19
Integrated Circuit And Method Of Manufacturing The Same App 20210057426 - PIAZZA; Fausto ; et al.	2021-02-25
Integrated circuit and method of manufacturing the same Grant 10,833,094 - Piazza , et al. November 10, 2	2020-11-10
Electronic Component Manufacturing Method App 20200098989 - Canvel; Yann ; et al.	2020-03-26
Metal shield trenches and metal substrate contacts supported within the premetallization dielectric (PMD) layer of an integrated circuit using a middle end of line (MEOL) process Grant 10,128,295 - Lagrasta , et al. November 13, 2	2018-11-13
Integrated Circuit And Method Of Manufacturing The Same App 20180233511 - PIAZZA; Fausto ; et al.	2018-08-16
Metal Shield Trenches And Metal Substrate Contacts Supported Within The Premetallization Dielectric (pmd) Layer Of An Integrated Circuit Using A Middle End Of Line (meol) Process App 20180158861 - Lagrasta; Sebastien ; et al.	2018-06-07
Integrated circuit and method of manufacturing the same Grant 9,978,764 - Piazza , et al. May 22, 2	2018-05-22
Metal Shield Trenches And Metal Substrate Contacts Supported Within The Premetallization Dielectric (pmd) Layer Of An Integrated Circuit Using A Middle End Of Line (meol) Process App 20180076250 - Lagrasta; Sebastien ; et al.	2018-03-15
Metal shield trenches and metal substrate contacts supported within the premetallization dielectric (PMD) layer of an integrated circuit using a middle end of line (MEOL) process Grant 9,917,126 - Lagrasta , et al. March 13, 2	2018-03-13
Integrated Circuit And Method Of Manufacturing The Same App 20170186759 - Piazza; Fausto ; et al.	2017-06-29
Production of spacers at flanks of a transistor gate Grant 9,543,409 - Arvet , et al. January 10, 2	2017-01-10
Production Of Spacers At Flanks Of A Transistor Gate App 20160079388 - ARVET; Christian ; et al.	2016-03-17

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