Lackey; David E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lackey; David E..The latest application filed is for "test path selection and test program generation for performance testing integrated circuit chips".

Company Profile

0.48.40

Lackey; David E. - Jericho VT US
Lackey; David E. - Essex Junction VT
Lackey; David E - Jericho VT
Lackey; David E. - Underhill VT
Lackey; David E. - Poughkeepsie NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and device for selectively adding timing margin in an integrated circuit Grant 8,589,843 - Lackey , et al. November 19, 2	2013-11-19
Test path selection and test program generation for performance testing integrated circuit chips Grant 8,543,966 - Bickford , et al. September 24, 2	2013-09-24
Method and device for selectively adding timing margin in an integrated circuit Grant 8,504,971 - Lackey , et al. August 6, 2	2013-08-06
Disposition of integrated circuits using performance sort ring oscillator and performance path testing Grant 8,490,040 - Bickford , et al. July 16, 2	2013-07-16
Method and device for selectively adding timing margin in an integrated circuit Grant 8,490,045 - Lackey , et al. July 16, 2	2013-07-16
Test Path Selection And Test Program Generation For Performance Testing Integrated Circuit Chips App 20130125073 - Bickford; Jeanne P. ; et al.	2013-05-16
Disposition Of Integrated Circuits Using Performance Sort Ring Oscillator And Performance Path Testing App 20130125076 - Bickford; Jeanne P. ; et al.	2013-05-16
Microcontroller for logic built-in self test (LBIST) Grant 8,423,847 - Grise , et al. April 16, 2	2013-04-16
Dense register array for enabling scan out observation of both L1 and L2 latches Grant 8,423,844 - Gillis , et al. April 16, 2	2013-04-16
Microcontroller For Logic Built-in Self Test (lbist) App 20120221910 - GRISE; Gary D. ; et al.	2012-08-30
Method and apparatus for a robust embedded interface Grant 8,239,715 - Eustis , et al. August 7, 2	2012-08-07
Dense Register Array For Enabling Scan Out Observation Of Both L1 And L2 Latches App 20120179944 - Gillis; Pamela S. ; et al.	2012-07-12
Microcontroller for logic built-in self test (LBIST) Grant 8,205,124 - Grise , et al. June 19, 2	2012-06-19
Method And Device For Selectively Adding Timing Margin In An Integrated Circuit App 20120124538 - LACKEY; David E. ; et al.	2012-05-17
Hold transition fault model and test generation method Grant 8,181,135 - Iyengar , et al. May 15, 2	2012-05-15
Method And Device For Selectively Adding Timing Margin In An Integrated Circuit App 20120112341 - LACKEY; David E. ; et al.	2012-05-10
Method And Device For Selectively Adding Timing Margin In An Integrated Circuit App 20120115256 - LACKEY; David E. ; et al.	2012-05-10
Method and device for selectively adding timing margin in an integrated circuit Grant 8,122,409 - Lackey , et al. February 21, 2	2012-02-21
LSSD compatibility for GSD unified global clock buffers Grant 8,117,579 - Warnock , et al. February 14, 2	2012-02-14
Avoiding race conditions at clock domain crossings in an edge based scan design Grant 7,996,739 - Lackey August 9, 2	2011-08-09
Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method Grant 7,996,807 - Grise , et al. August 9, 2	2011-08-09
Design structure and apparatus for a robust embedded interface Grant 7,937,632 - Eustis , et al. May 3, 2	2011-05-03
Avoiding Race Conditions At Clock Domain Crossings In An Edge Based Scan Design App 20110066904 - Lackey; David E.	2011-03-17
Hold Transition Fault Model and Test Generation Method App 20110055650 - Iyengar; Vikram ; et al.	2011-03-03
System and method for generating at-speed structural tests to improve process and environmental parameter space coverage Grant 7,856,607 - Grise , et al. December 21, 2	2010-12-21
Apparatus and method for selectively implementing launch off scan capability in at speed testing Grant 7,721,170 - Grise , et al. May 18, 2	2010-05-18
Structure And Apparatus For A Robust Embedded Interface App 20090319841 - Eustis; Steven M. ; et al.	2009-12-24
Method And Apparatus For A Robust Embedded Interface App 20090319818 - Eustis; Steven M. ; et al.	2009-12-24
IC chip at-functional-speed testing with process coverage evaluation Grant 7,620,921 - Foreman , et al. November 17, 2	2009-11-17
Integrated Test Waveform Generator (twg) And Customer Waveform Generator (cwg), Design Structure And Method App 20090265677 - Grise; Gary D. ; et al.	2009-10-22
LSSD compatibility for GSD unified global clock buffers App 20090199036 - Warnock; James D. ; et al.	2009-08-06
Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility Grant 7,560,964 - Lackey , et al. July 14, 2	2009-07-14
Critical Path Selection For At-speed Test App 20090150844 - Iyengar; Vikram ; et al.	2009-06-11
System And Method For Generating At-speed Structural Tests To Improve Process And Environmental Parameter Space Coverage App 20090119629 - Grise; Gary D. ; et al.	2009-05-07
Testing of multiple asynchronous logic domains Grant 7,529,294 - Grise , et al. May 5, 2	2009-05-05
Apparatus And Method For Selectively Implementing Launch Off Scan Capability In At Speed Testing App 20090106608 - Grise; Gary D. ; et al.	2009-04-23
Method And Device For Selectively Adding Timing Margin In An Integrated Circuit App 20090094565 - Lackey; David E. ; et al.	2009-04-09
Microcontroller For Logic Built-in Self Test (lbist) App 20090055696 - Grise; Gary D. ; et al.	2009-02-26
Microcontroller for logic built-in self test (LBIST) Grant 7,490,280 - Grise , et al. February 10, 2	2009-02-10
Negative edge flip-flops for muxscan and edge clock compatible LSSD Grant 7,484,149 - Lackey January 27, 2	2009-01-27
Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility Grant 7,482,851 - Lackey , et al. January 27, 2	2009-01-27
Ic Chip At-functional-speed Testing With Process Coverage Evaluation App 20080270953 - Foreman; Eric A. ; et al.	2008-10-30
Negative Edge Flip-flops For Muxscan And Edge Clock Compatible Lssd App 20080270861 - Lackey; David E.	2008-10-30
Methods Of Synchronous Digital Operation And Scan Based Testing Of An Integrated Circuit Using Negative Edge Flip-flops For Muxscan And Edge Clock Compatible Lssd App 20080270863 - Lackey; David E.	2008-10-30
Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer Grant 7,435,990 - Keller , et al. October 14, 2	2008-10-14
Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer Grant 7,381,986 - Keller , et al. June 3, 2	2008-06-03
Latch And Clock Structures For Enabling Race-reduced Mux Scan And Lssd Co-compatibility App 20080042712 - LACKEY; David E. ; et al.	2008-02-21
Negative Edge Flip-flops For Muxscan And Edge Clock Compatible Lssd App 20070220382 - Lackey; David E.	2007-09-20
Microcontroller For Logic Built-in Self Test (lbist) App 20070204193 - Grise; Gary D. ; et al.	2007-08-30
Testing Of Multiple Asynchronous Logic Domains App 20070204194 - Grise; Gary Douglas ; et al.	2007-08-30
Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer App 20060284174 - Keller; Brion L. ; et al.	2006-12-21
Nested voltage island architecture Grant 7,131,074 - Bednar , et al. October 31, 2	2006-10-31
Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility App 20060208783 - Lackey; David E. ; et al.	2006-09-21
Voltage island chip implementation Grant 6,883,152 - Bednar , et al. April 19, 2	2005-04-19
Method for insertion of test points into integrated logic circuit designs Grant 6,865,723 - Lackey March 8, 2	2005-03-08
Pipeline array Grant 6,856,270 - Farmer , et al. February 15, 2	2005-02-15
Nested Voltage Island Architecture App 20050010887 - Bednar, Thomas R. ; et al.	2005-01-13
Voltage island chip implementation App 20040243958 - Bednar, Thomas R. ; et al.	2004-12-02
Voltage island chip implementation Grant 6,820,240 - Bednar , et al. November 16, 2	2004-11-16
Method for testing integrated logic circuits Grant 6,804,803 - Barnhart , et al. October 12, 2	2004-10-12
Concurrent logical and physical construction of voltage islands for mixed supply voltage designs Grant 6,792,582 - Cohn , et al. September 14, 2	2004-09-14
Voltage island design planning Grant 6,779,163 - Bednar , et al. August 17, 2	2004-08-17
An Arrangement For Testing Semiconductor Chips While Incorporated On A Semiconductor Wafer App 20040135231 - Keller, Brion L. ; et al.	2004-07-15
Method for insertion of test points into integrated circuit logic designs Grant 6,745,373 - Lackey June 1, 2	2004-06-01
Method for insertion of test points into integrated logic circuit designs App 20040098686 - Lackey, David E.	2004-05-20
Global voltage buffer for voltage islands Grant 6,731,154 - Bednar , et al. May 4, 2	2004-05-04
Voltage island design planning App 20040060024 - Bednar, Thomas R. ; et al.	2004-03-25
Voltage island chip implementation App 20040060023 - Bednar, Thomas R. ; et al.	2004-03-25
Global voltage buffer for voltage islands App 20030206051 - Bednar, Thomas Richard ; et al.	2003-11-06
Method of automatic latch insertion for testing application specific integrated circuits Grant 6,636,995 - Dean , et al. October 21, 2	2003-10-21
Latch clustering for power optimization Grant 6,609,228 - Bergeron , et al. August 19, 2	2003-08-19
Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox Grant 6,577,156 - Anand , et al. June 10, 2	2003-06-10
Apparatus for assisting backside focused ion beam device modification App 20030015671 - Lackey, David E. ; et al.	2003-01-23
Method for testing integrated logic circuits App 20020147559 - Barnhart, Carl F. ; et al.	2002-10-10
Method for insertion of test points into integrated logic circuit designs App 20020116690 - Lackey, David E.	2002-08-22
Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox App 20020101777 - Anand, Darren L. ; et al.	2002-08-01
Double-edge-triggered flip-flop providing two data transitions per clock cycle Grant 6,300,809 - Gregor , et al. October 9, 2	2001-10-09
Integrated circuit device with improved clock signal control Grant 5,783,960 - Lackey July 21, 1	1998-07-21
Logic simulation using a hardware accelerator together with an automated error event isolation and trace facility Grant 5,146,460 - Ackerman , et al. September 8, 1	1992-09-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.