Lachenmann; Susanne

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lachenmann; Susanne.The latest application filed is for "semiconductor product having a semiconductor substrate and a test structure and method".

Company Profile

0.4.6

Lachenmann; Susanne - Munich DE
Lachenmann; Susanne - Munchen DE
Lachenmann; Susanne - Muenchen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor wafer with test structure Grant 7,372,072 - Winter , et al. May 13, 2	2008-05-13
Semiconductor product having a semiconductor substrate and a test structure and method Grant 7,205,567 - Felber , et al. April 17, 2	2007-04-17
Test structure for a single-sided buried strap DRAM memory cell array Grant 7,126,154 - Rosskopf , et al. October 24, 2	2006-10-24
Semiconductor product having a semiconductor substrate and a test structure and method App 20060175647 - Felber; Andreas ; et al.	2006-08-10
Kerf with improved fill routine App 20060157702 - Sukman-Prahofer; Sibina ; et al.	2006-07-20
Semiconductor wafer with test structure App 20060157700 - Winter; Ramona ; et al.	2006-07-20
Semiconductor wafer with a test structure, and method App 20060138411 - Lachenmann; Susanne ; et al.	2006-06-29
Test structure for a single-sided buried strap DRAM memory cell array App 20050051765 - Rosskopf, Valentin ; et al.	2005-03-10
Test structure for measuring a junction resistance in a DRAM memory cell array Grant 6,856,562 - Lachenmann , et al. February 15, 2	2005-02-15
Test structure for measuring a junction resistance in a DRAM memory cell array App 20040057292 - Lachenmann, Susanne ; et al.	2004-03-25

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