KWAK; Kun-Ho

Patent Applications and Registrations

Patent applications and USPTO patent grants for KWAK; Kun-Ho.The latest application filed is for "semiconductor cell structure, semiconductor device including semiconductor cell structure, and semiconductor module including semiconductor device".

Company Profile

0.11.15

KWAK; Kun-Ho - Hwaseong-si KR
Kwak; Kun-Ho - Yongin-si KR
Kwak; Kun-Ho - Gyeonggi-do KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor Cell Structure, Semiconductor Device Including Semiconductor Cell Structure, And Semiconductor Module Including Semiconductor Device App 20110198706 - KWAK; Kun-Ho ; et al.	2011-08-18
Semiconductor devices having thin film transistors and methods of fabricating the same Grant 7,719,033 - Jeong , et al. May 18, 2	2010-05-18
Semiconductor Memory Device and Method for Arranging and Manufacturing the Same App 20090224330 - Hong; Chang Min ; et al.	2009-09-10
Node contact structures in semiconductor devices Grant 7,521,715 - Jang , et al. April 21, 2	2009-04-21
Semiconductor integrated circuits with stacked node contact structures Grant 7,479,673 - Jang , et al. January 20, 2	2009-01-20
Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same Grant 7,417,286 - Kim , et al. August 26, 2	2008-08-26
Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter Grant 7,387,919 - Kwak , et al. June 17, 2	2008-06-17
Semiconductor Integrated Circuits With Stacked Node Contact Structures App 20080023728 - Jang; Jae-Hoon ; et al.	2008-01-31
Methods of fabricating semiconductor devices having thin film transistors Grant 7,312,110 - Kwak , et al. December 25, 2	2007-12-25
Methods Of Fabricating Semiconductor Integrated Circuits Using Selective Epitaxial Growth And Partial Planarization Techniques And Semiconductor Integrated Circuits Fabricated Thereby App 20070241335 - KWAK; Kun-Ho ; et al.	2007-10-18
Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns Grant 7,276,404 - Kim , et al. October 2, 2	2007-10-02
Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby Grant 7,276,421 - Kim , et al. October 2, 2	2007-10-02
Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques Grant 7,247,528 - Kwak , et al. July 24, 2	2007-07-24
Methods of forming semiconductor devices using an etch stop layer Grant 7,202,180 - Koh , et al. April 10, 2	2007-04-10
Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns App 20070042554 - Kim; Sung-Jin ; et al.	2007-02-22
SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same Grant 7,135,746 - Kim , et al. November 14, 2	2006-11-14
Semiconductor devices having thin film transistors and methods of fabricating the same App 20060237725 - Jeong; Jae-Hun ; et al.	2006-10-26
Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter App 20060115944 - Kwak; Kun-Ho ; et al.	2006-06-01
Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same App 20060102959 - Kim; Sung-Jin ; et al.	2006-05-18
SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same App 20060097328 - Kim; Sung-Jin ; et al.	2006-05-11
Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby App 20060097319 - Kim; Jong-Hyuk ; et al.	2006-05-11
Methods of fabricating semiconductor devices having thin film transistors App 20050221544 - Kwak, Kun-Ho ; et al.	2005-10-06
Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby App 20050184292 - Kwak, Kun-Ho ; et al.	2005-08-25
Semiconductor integrated circuits with stacked node contact structures and methods of fabricating such devices App 20050179061 - Jang, Jae-Hoon ; et al.	2005-08-18
Node contact structures in semiconductor devices and methods of fabricating the same App 20050151276 - Jang, Jae-Hoon ; et al.	2005-07-14
Methods of forming semiconductor devices using an etch stop layer App 20040121612 - Koh, Kwang-Ok ; et al.	2004-06-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.