Kusko; Mary P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kusko; Mary P..The latest application filed is for "diagnostic enhancement for multiple instances of identical structures".

Company Profile

29.71.65

Kusko; Mary P. - Hopewell Junction NY
Kusko; Mary P. - Poughkeepsie NY
Kusko; Mary P. - Poughkeepskie NY
Kusko; Mary P. - Hopwell Junction NY
Kusko; Mary P - Hopewell Junction NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Diagnostic enhancement for multiple instances of identical structures Grant 11,378,623 - Douskey , et al. July 5, 2	2022-07-05
Diagnostic Enhancement For Multiple Instances Of Identical Structures App 20220178996 - DOUSKEY; Steven Michael ; et al.	2022-06-09
User Privacy For Autonomous Vehicles App 20220027501 - Kusko; Mary P. ; et al.	2022-01-27
Operating pulsed latches on a variable power supply Grant 11,112,854 - Douskey , et al. September 7, 2	2021-09-07
Dynamic weight selection process for logic built-in self test Grant 11,112,457 - Kusko , et al. September 7, 2	2021-09-07
Logic built-in self test dynamic weight selection method Grant 11,079,433 - Motika , et al. August 3, 2	2021-08-03
Logic Built-in Self Test Dynamic Weight Selection Method App 20210156911 - Motika; Franco ; et al.	2021-05-27
Dynamic Weight Selection Process For Logic Built-in Self Test App 20210156910 - Kusko; Mary P. ; et al.	2021-05-27
Dynamically power noise adaptive automatic test pattern generation Grant 10,816,599 - Douskey , et al. October 27, 2	2020-10-27
Built-in device testing of integrated circuits Grant 10,768,230 - Casatuta , et al. Sep	2020-09-08
Logic built in self test circuitry for use in an integrated circuit with scan chains Grant 10,746,794 - Bhamidipati , et al. A	2020-08-18
Logic built in self test circuitry for use in an integrated circuit with scan chains Grant 10,739,401 - Bhamidipati , et al. A	2020-08-11
Dynamically Power Noise Adaptive Automatic Test Pattern Generation App 20200225283 - DOUSKEY; Steven M. ; et al.	2020-07-16
Logic built in self test circuitry for use in an integrated circuit with scan chains Grant 10,649,028 - Bhamidipati , et al.	2020-05-12
Non-destructive recirculation test support for integrated circuits Grant 10,613,142 - Kusko , et al.	2020-04-07
Identification of unknown sources for logic built-in self test in verification Grant 10,598,727 - Bhamidipati , et al.	2020-03-24
Functional diagnostics based on dynamic selection of alternate clocking Grant 10,585,142 - Kusko , et al.	2020-03-10
Circuit structures to resolve random testability Grant 10,545,190 - GopalaKrishnaSetty , et al. Ja	2020-01-28
Functional diagnostics based on dynamic selection of alternate clocking Grant 10,545,188 - Kusko , et al. Ja	2020-01-28
Circuit structures to resolve random testability Grant 10,527,674 - GopalaKrishnaSetty , et al. J	2020-01-07
Synthesis for random testability using unreachable states in integrated circuits Grant 10,502,782 - Kravets , et al. Dec	2019-12-10
Operating Pulsed Latches On A Variable Power Supply App 20190286221 - DOUSKEY; STEVEN M. ; et al.	2019-09-19
Operating pulsed latches on a variable power supply Grant 10,386,912 - Douskey , et al. A	2019-08-20
Minimization of over-masking in an on product multiple input signature register (OPMISR) Grant 10,379,159 - Douskey , et al. A	2019-08-13
Removal of over-masking in an on product multiple input signature register (OPMISR) test Grant 10,371,749 - Douskey , et al.	2019-08-06
Minimization of over-masking in an on product multiple input signature register (OPMISR) Grant 10,371,750 - Douskey , et al.	2019-08-06
Physically aware scan diagnostic logic and power saving circuit insertion Grant 10,371,747 - Huott , et al.	2019-08-06
Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading Grant 10,345,380 - Douskey , et al. July 9, 2	2019-07-09
Synthesis For Random Testability Using Unreachable States In Integrated Circuits App 20190146031 - Kravets; Victor N. ; et al.	2019-05-16
Iterative N-detect based logic diagnostic technique Grant 10,254,336 - Kusko , et al.	2019-04-09
Structurally assisted functional test and diagnostics for integrated circuits Grant 10,247,776 - Kusko , et al.	2019-04-02
Functional Diagnostics Based On Dynamic Selection Of Alternate Clocking App 20190094298 - Kusko; Mary P. ; et al.	2019-03-28
Functional Diagnostics Based On Dynamic Selection Of Alternate Clocking App 20190094297 - Kusko; Mary P. ; et al.	2019-03-28
Circuit Structures To Resolve Random Testability App 20190056449 - GopalaKrishnaSetty; Raghu G. ; et al.	2019-02-21
Circuit Structures To Resolve Random Testability App 20190056450 - GopalaKrishnaSetty; Raghu G. ; et al.	2019-02-21
Scan chain latency reduction Grant 10,168,386 - Antony , et al. J	2019-01-01
Dynamic fault model generation for diagnostics simulation and pattern generation Grant 10,169,510 - Kusko , et al. J	2019-01-01
Logic Built In Self Test Circuitry For Use In An Integrated Circuit With Scan Chains App 20180306858 - Bhamidipati; Satya R.S. ; et al.	2018-10-25
Bitwise rotating scan section for microelectronic chip testing and diagnostics Grant 10,107,860 - Cohen , et al. October 23, 2	2018-10-23
Logic built in self test circuitry for use in an integrated circuit with scan chains Grant 10,088,524 - Bhamidipati , et al. October 2, 2	2018-10-02
Iterative N-detect Based Logic Diagnostic Technique App 20180252769 - KUSKO; Mary P. ; et al.	2018-09-06
Portion isolation architecture for chip isolation test Grant 10,067,183 - Douskey , et al. September 4, 2	2018-09-04
Adjusting latency in a scan cell Grant 10,060,971 - Douskey , et al. August 28, 2	2018-08-28
Non-destructive Recirculation Test Support For Integrated Circuits App 20180238964 - Kusko; Mary P. ; et al.	2018-08-23
Structurally Assisted Functional Test And Diagnostics For Integrated Circuits App 20180238962 - Kusko; Mary P. ; et al.	2018-08-23
Scan Chain Latency Reduction App 20180203066 - Antony; George ; et al.	2018-07-19
Scan Chain Latency Reduction App 20180203064 - Antony; George ; et al.	2018-07-19
Iterative N-detect based logic diagnostic technique Grant 10,024,910 - Kusko , et al. July 17, 2	2018-07-17
Operating Pulsed Latches On A Variable Power Supply App 20180196497 - DOUSKEY; STEVEN M. ; et al.	2018-07-12
Reducing power requirements and switching during logic built-in-self-test and scan test Grant 10,018,672 - Bhamidipati , et al. July 10, 2	2018-07-10
Reducing power requirements and switching during logic built-in-self-test and scan test Grant 10,018,671 - Bhamidipati , et al. July 10, 2	2018-07-10
Adjusting latency in a scan cell Grant 10,001,523 - Douskey , et al. June 19, 2	2018-06-19
Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry Grant 9,929,749 - Fee , et al. March 27, 2	2018-03-27
Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry Grant 9,923,579 - Fee , et al. March 20, 2	2018-03-20
Dynamic Fault Model Generation For Diagnostics Simulation And Pattern Generation App 20180075170 - KUSKO; Mary P. ; et al.	2018-03-15
Bypassing an encoded latch on a chip during a test-pattern scan Grant 9,915,701 - Fee , et al. March 13, 2	2018-03-13
Bypassing an encoded latch on a chip during a test-pattern scan Grant 9,910,090 - Fee , et al. March 6, 2	2018-03-06
Adjusting Latency In A Scan Cell App 20180052198 - DOUSKEY; Steven M. ; et al.	2018-02-22
Adjusting Latency In A Scan Cell App 20180052199 - DOUSKEY; Steven M. ; et al.	2018-02-22
Dynamic fault model generation for diagnostics simulation and pattern generation Grant 9,852,245 - Kusko , et al. December 26, 2	2017-12-26
Portion Isolation Architecture For Chip Isolation Test App 20170363683 - Douskey; Steven M. ; et al.	2017-12-21
Bitwise Rotating Scan Section For Microelectronic Chip Testing And Diagnostics App 20170363684 - Cohen; Todd L. ; et al.	2017-12-21
Built-in Device Testing Of Integrated Circuits App 20170343601 - Casatuta; Robert M. ; et al.	2017-11-30
Identification Of Unknown Sources For Logic Built-in Self Test In Verification App 20170285104 - Bhamidipati; Satya R. S. ; et al.	2017-10-05
Bypassing An Encoded Latch On A Chip During A Test-pattern Scan App 20170261550 - Fee; Michael ; et al.	2017-09-14
Clock Path Technique For Using On-chip Circuitry To Generate A Correct Encode Pattern To Test The On-chip Circuitry App 20170261557 - Fee; Michael ; et al.	2017-09-14
Clock Path Technique For Using On-chip Circuitry To Generate A Correct Encode Pattern To Test The On-chip Circuitry App 20170261556 - Fee; Michael ; et al.	2017-09-14
Bypassing An Encoded Latch On A Chip During A Test-pattern Scan App 20170261555 - Fee; Michael ; et al.	2017-09-14
Physically Aware Scan Diagnostic Logic And Power Saving Circuit Insertion App 20170254851 - HUOTT; WILLIAM V. ; et al.	2017-09-07
Physically Aware Scan Diagnostic Logic And Power Saving Circuit Insertion App 20170254850 - HUOTT; WILLIAM V. ; et al.	2017-09-07
Collecting diagnostic data from chips Grant 9,746,516 - Douskey , et al. August 29, 2	2017-08-29
Iterative N-detect Based Logic Diagnostic Technique App 20170219651 - Kusko; Mary P. ; et al.	2017-08-03
Dynamic Fault Model Generation For Diagnostics Simulation And Pattern Generation App 20170199946 - Kusko; Mary P. ; et al.	2017-07-13
Logic Built In Self Test Circuitry For Use In An Integrated Circuit With Scan Chains App 20170192057 - BHAMIDIPATI; SATYA R.S. ; et al.	2017-07-06
Logic Built In Self Test Circuitry For Use In An Integrated Circuit With Scan Chains App 20170192055 - Bhamidipati; Satya R.S. ; et al.	2017-07-06
Logic Built In Self Test Circuitry For Use In An Integrated Circuit With Scan Chains App 20170192054 - Bhamidipati; Satya R.S. ; et al.	2017-07-06
Identification of unknown sources for logic built-in self test in verification Grant 9,689,920 - Bhamidipati , et al. June 27, 2	2017-06-27
Reducing Power Requirements And Switching During Logic Built-in-self-test And Scan Test App 20170176532 - Bhamidipati; Satya Rama S. ; et al.	2017-06-22
Reducing Power Requirements And Switching During Logic Built-in-self-test And Scan Test App 20170176531 - Bhamidipati; Satya Rama S. ; et al.	2017-06-22
Reducing power requirements and switching during logic built-in-self-test and scan test Grant 9,651,623 - Bhamidipati , et al. May 16, 2	2017-05-16
Reducing power requirements and switching during logic built-in-self-test and scan test Grant 9,651,616 - Bhamidipati , et al. May 16, 2	2017-05-16
Reducing Power Requirements And Switching During Logic Built-in-self-test And Scan Test App 20170074935 - Bhamidipati; Satya Rama S. ; et al.	2017-03-16
Reducing Power Requirements And Switching During Logic Built-in-self-test And Scan Test App 20170074934 - Bhamidipati; Satya Rama S. ; et al.	2017-03-16
Optimizing generation of test configurations for built-in self-testing Grant 9,588,177 - Atwood , et al. March 7, 2	2017-03-07
Physically aware insertion of diagnostic circuit elements Grant 9,557,381 - Huott , et al. January 31, 2	2017-01-31
Dynamic fault model generation for diagnostics simulation and pattern generation Grant 9,552,449 - Kusko , et al. January 24, 2	2017-01-24
Collecting Diagnostic Data From Chips App 20160238656 - Douskey; Steven M. ; et al.	2016-08-18
Shared channel masks in on-product test compression system Grant 9,378,318 - Douskey , et al. June 28, 2	2016-06-28
Identification Of Unknown Sources For Logic Built-in Self Test In Verification App 20160178696 - Bhamidipati; Satya R. S. ; et al.	2016-06-23
Collecting diagnostic data from chips Grant 9,372,232 - Douskey , et al. June 21, 2	2016-06-21
Shared channel masks in on-product test compression system Grant 9,355,203 - Douskey , et al. May 31, 2	2016-05-31
Implementing MISR compression methods for test time reduction Grant 9,297,856 - Douskey , et al. March 29, 2	2016-03-29
Design-based weighting for logic built-in self-test Grant 9,292,398 - Cook , et al. March 22, 2	2016-03-22
Design-Based weighting for logic built-in self-test Grant 9,292,399 - Cook , et al. March 22, 2	2016-03-22
Managing chip testing data Grant 9,285,423 - Douskey , et al. March 15, 2	2016-03-15
Identification of unknown sources for logic built-in self test in verification Grant 9,268,892 - Bhamidipati , et al. February 23, 2	2016-02-23
Chip testing with exclusive OR Grant 9,151,800 - Douskey , et al. October 6, 2	2015-10-06
Hierarchal test block test pattern reduction in on-product test compression system Grant 9,134,375 - Douskey , et al. September 15, 2	2015-09-15
Hierarchal test block test pattern reduction in on-product test compression system Grant 9,134,373 - Douskey , et al. September 15, 2	2015-09-15
Shared Channel Masks In On-product Test Compression System App 20150254387 - Douskey; Steven M. ; et al.	2015-09-10
Shared Channel Masks In On-product Test Compression System App 20150254390 - Douskey; Steven M. ; et al.	2015-09-10
Hierarchal Test Block Test Pattern Reduction In On-product Test Compression System App 20150253382 - Douskey; Steven M. ; et al.	2015-09-10
Hierarchal Test Block Test Pattern Reduction In On-product Test Compression System App 20150253383 - Douskey; Steven M. ; et al.	2015-09-10
Chip testing with exclusive OR Grant 9,110,135 - Douskey , et al. August 18, 2	2015-08-18
Managing Chip Testing Data App 20150168490 - Douskey; Steven M. ; et al.	2015-06-18
Design-based Weighting For Logic Built-in Self-test App 20150168489 - Cook; Gregory J. ; et al.	2015-06-18
Design-based Weighting For Logic Built-in Self-test App 20150169423 - Cook; Gregory J. ; et al.	2015-06-18
Collecting Diagnostic Data From Chips App 20150168491 - Douskey; Steven M. ; et al.	2015-06-18
Implementing Misr Compression Methods For Test Time Reduction App 20150113348 - Douskey; Steven M. ; et al.	2015-04-23
Chip Testing With Exclusive Or App 20150089311 - Douskey; Steven M. ; et al.	2015-03-26
Chip Testing With Exclusive Or App 20150089312 - Douskey; Steven M. ; et al.	2015-03-26
Automated file relocation Grant 8,768,985 - Kusko , et al. July 1, 2	2014-07-01
Insertion of faults in logic model used in simulation Grant 8,566,059 - Desineni , et al. October 22, 2	2013-10-22
Automated termination of selected software applications in response system events Grant 8,255,928 - Kusko , et al. August 28, 2	2012-08-28
Automated File Relocation App 20120143828 - KUSKO; MARY P. ; et al.	2012-06-07
Automated file relocation Grant 8,176,105 - Kusko , et al. May 8, 2	2012-05-08
Method and apparatus for improving random pattern testing of logic structures Grant 8,095,837 - Kusko , et al. January 10, 2	2012-01-10
Insertion Of Faults In Logic Model Used In Simulation App 20110137602 - Desineni; Rao H. ; et al.	2011-06-09
Apparatus and method for improved test controllability and observability of random resistant logic Grant 7,882,454 - Kusko , et al. February 1, 2	2011-02-01
Method for enhancing the diagnostic accuracy of a VLSI chip Grant 7,831,863 - Kusko , et al. November 9, 2	2010-11-09
Automated Termination of Selected Software Applications in Response to System Events App 20100211950 - Kusko; Mary P. ; et al.	2010-08-19
Automated File Relocation App 20100146019 - Kusko; Mary P. ; et al.	2010-06-10
Enhancing Computer Screen Security Using Customized Control Of Displayed Content Area App 20090273562 - Baliga; Priya ; et al.	2009-11-05
Apparatus And Method For Improved Test Controllability And Observability Of Random Resistant Logic App 20090271671 - Kusko; Mary P. ; et al.	2009-10-29
Apparatus, System, And Method For Managing Collaborative Sharing By Invitees To A Meeting Of Their Meeting Status App 20090254615 - Baliga; Priya ; et al.	2009-10-08
Method And Apparatus For Improving Random Pattern Testing Of Logic Structures App 20090240995 - Kusko; Mary P. ; et al.	2009-09-24
Method For Enhancing The Diagnostic Accuracy Of A Vlsi Chip App 20080172576 - Kusko; Mary P. ; et al.	2008-07-17
Iterative Test Generation And Diagnostic Method Based On Modeled And Unmodeled Faults App 20080115029 - Kusko; Mary P. ; et al.	2008-05-15
Static And Dynamic Learning Test Generation Method App 20070260926 - Forlenza; Donato O. ; et al.	2007-11-08
Method and apparatus for facilitating random pattern testing of logic structures Grant 6,836,865 - Kusko , et al. December 28, 2	2004-12-28
Method and apparatus for programmable LBIST channel weighting Grant 6,671,838 - Koprowski , et al. December 30, 2	2003-12-30
Method and apparatus for facilitating random pattern testing of logic structures App 20030070127 - Kusko, Mary P. ; et al.	2003-04-10
Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis Grant 6,442,720 - Koprowski , et al. August 27, 2	2002-08-27
Look ahead scan chain diagnostic method Grant 6,308,290 - Forlenza , et al. October 23, 2	2001-10-23

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