loadpatents
name:-0.02679705619812
name:-0.028298854827881
name:-0.00055789947509766
Kurihara; Toshihiko Patent Filings

Kurihara; Toshihiko

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kurihara; Toshihiko.The latest application filed is for "vending machine having a commodity column".

Company Profile
0.21.18
  • Kurihara; Toshihiko - Isesaki JP
  • Kurihara; Toshihiko - Isesaki-shi JP
  • Kurihara; Toshihiko - Hadano-shi JP
  • Kurihara; Toshihiko - Hadano JP
  • Kurihara; Toshihiko - Kanagawa-ken JP
  • Kurihara; Toshihiko - Saitama JP
  • Kurihara; Toshihiko - Tokorozawa-City Saitama JP
  • Kurihara; Toshihiko - Tokorozawa JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Vending machine having a commodity column
Grant 7,886,932 - Yanagisawa , et al. February 15, 2
2011-02-15
Vending Machine Having A Commodity Column
App 20080302813 - Yanagisawa; Yuuki ;   et al.
2008-12-11
Commodity Column For Vending Machine
App 20080296314 - YANAGISAWA; Yuuki ;   et al.
2008-12-04
Commodity Carrying Out Device
App 20080290108 - Tsunoda; Masaru ;   et al.
2008-11-27
Commodity Carrying Out Device
App 20080283545 - Tsunoda; Masaru ;   et al.
2008-11-20
Apparatus For Conveying And Storing Articles
App 20080131251 - Sato; Naoto ;   et al.
2008-06-05
Data processor having cache memory
App 20070233959 - Hotta; Takashi ;   et al.
2007-10-04
Data processor having cache memory
Grant 7,240,159 - Hotta , et al. July 3, 2
2007-07-03
Method for measuring memory latency in a hierarchical memory system
Grant 7,051,177 - Le , et al. May 23, 2
2006-05-23
Analyzing instruction completion delays in a processor
Grant 7,047,398 - Kurihara , et al. May 16, 2
2006-05-16
Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching
Grant 7,028,159 - Matsubara , et al. April 11, 2
2006-04-11
Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching
Grant 7,028,160 - Matsubara , et al. April 11, 2
2006-04-11
Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters
Grant 6,970,999 - Kurihara , et al. November 29, 2
2005-11-29
Speculative counting of performance events with rewind counter
Grant 6,910,120 - Le , et al. June 21, 2
2005-06-21
Data processor having cache memory
App 20050102472 - Hotta, Takashi ;   et al.
2005-05-12
Data processor having cache memory
Grant 6,848,027 - Hotta , et al. January 25, 2
2005-01-25
Cycles per instruction stack in a computer processor
App 20040025146 - Kurihara, Toshihiko ;   et al.
2004-02-05
Speculative counting of performance events with rewind counter
App 20040024996 - Le, Hung Qui ;   et al.
2004-02-05
Method and system for identifying instruction completion delays in a processor
App 20040024994 - Kurihara, Toshihiko ;   et al.
2004-02-05
Method for measuring memory latency in a hierarchical memory system
App 20040024982 - Le, Hung Qui ;   et al.
2004-02-05
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching
App 20030208659 - Matsubara, Kenji ;   et al.
2003-11-06
Data processor having cache memory
App 20030204676 - Hotta, Takashi ;   et al.
2003-10-30
Processing device which prefetches instruction having indicator bits specifying a quantity of operand data for prefetching
App 20030196045 - Matsubara, Kenji ;   et al.
2003-10-16
Processing device which prefetches instructions having indicator bits specifying cache levels for prefetching
Grant 6,598,126 - Matsubara , et al. July 22, 2
2003-07-22
Information processing system with prefetch instructions having indicator bits specifying a quantity of operand data for prefetching
Grant 6,598,127 - Matsubara , et al. July 22, 2
2003-07-22
Data processor having cache memory
Grant 6,587,927 - Hotta , et al. July 1, 2
2003-07-01
Information Processing System With Prefetch Instructions Having Indicator Bits Specifying Cache Levels For Prefetching
App 20020083272 - Matsubara, Kenji ;   et al.
2002-06-27
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching
App 20020083273 - Matsubara, Kenji ;   et al.
2002-06-27
Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching
Grant 6,381,679 - Matsubara , et al. April 30, 2
2002-04-30
Data processor having cache memory
App 20010037432 - Hotta, Takashi ;   et al.
2001-11-01
Cache memory apparatus and data processing system
App 20010032297 - Morikawa, Naoto ;   et al.
2001-10-18
Article providing apparatus which has excellent loading capacity and enables reduction in its installation area
Grant 6,168,246 - Kurihara January 2, 2
2001-01-02
Information processing unit and method for controlling a hierarchical cache utilizing indicator bits to control content of prefetching operations
Grant 6,131,145 - Matsubara , et al. October 10, 2
2000-10-10
Data processor with variable types of cache memories
Grant 5,848,432 - Hotta , et al. December 8, 1
1998-12-08
Optical pickup with bilateral and vertical symmetry
Grant 5,165,088 - Suzuki , et al. November 17, 1
1992-11-17
Information recording disk playback apparatus
Grant 5,105,414 - Funabashi , et al. April 14, 1
1992-04-14
Disk drive with means to play either side of a disk
Grant 5,105,418 - Kenmotsu , et al. April 14, 1
1992-04-14
Lens driving device for an optical pickup unit with simplified construction
Grant 4,679,904 - Kurihara July 14, 1
1987-07-14
Pick-up device positioning arrangement in an information disc player
Grant 4,545,003 - Hirano , et al. October 1, 1
1985-10-01

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