Kuribayashi; Mototaka
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kuribayashi; Mototaka.The latest application filed is for "method of reducing circuit data, method of simulating circuit, and medium for storing circuit data reduction program".
- Kuribayashi; Mototaka - Tokyo JP
- Kuribayashi; Mototaka - Kanagawa-ken JP
- Kuribayashi; Mototaka - Kawasaki JP
| Patent | Date |
|---|---|
| Method of reducing circuit data, method of simulating circuit, and medium for storing circuit data reduction program Grant 6,374,205 - Kuribayashi , et al. April 16, 2 | 2002-04-16 |
| Pattern matching method, timing analysis method and timing analysis device Grant 6,223,333 - Kuribayashi , et al. April 24, 2 | 2001-04-24 |
| Automatic layout design method of wirings in integrated circuit using hierarchical algorithm Grant 5,583,788 - Kuribayashi December 10, 1 | 1996-12-10 |
| Semiconductor integrated circuit and method of manufacturing the same Grant 5,012,427 - Kuribayashi April 30, 1 | 1991-04-30 |
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