Kuo; Yung-Liang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kuo; Yung-Liang.The latest application filed is for "method and system for wafer-level testing".

Company Profile

1.5.5

Kuo; Yung-Liang - Hsinchu TW
Kuo; Yung-Liang - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and device for wafer-level testing Grant 11,448,692 - He , et al. September 20, 2	2022-09-20
Method And System For Wafer-level Testing App 20210311110 - HE; JUN ; et al.	2021-10-07
Method and system for wafer-level testing Grant 11,073,551 - He , et al. July 27, 2	2021-07-27
Method And Device For Wafer-level Testing App 20210199710 - HE; JUN ; et al.	2021-07-01
Method And System For Wafer-level Testing App 20200064396 - HE; JUN ; et al.	2020-02-27
Universal array type probe card design for semiconductor device testing Grant 8,248,091 - Cheng , et al. August 21, 2	2012-08-21
Chip-probing and bumping solutions for stacked dies having through-silicon vias Grant 7,781,235 - Luo , et al. August 24, 2	2010-08-24
Test structures for stacking dies having through-silicon vias Grant 7,598,523 - Luo , et al. October 6, 2	2009-10-06
Test structures for stacking dies having through-silicon vias App 20080272372 - Luo; Wen-Liang ; et al.	2008-11-06
Chip-probing and bumping solutions for stacked dies having through-silicon vias App 20080153187 - Luo; Wen-Liang ; et al.	2008-06-26

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