Kuo; Harry H.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kuo; Harry H..The latest application filed is for "high speed zero dc power programmable logic device (pld) architecture".
- Kuo; Harry H. - San Jose CA
| Patent | Date |
|---|---|
| High speed zero DC power programmable logic device (PLD) architecture Grant 6,809,550 - Pathak , et al. October 26, 2 | 2004-10-26 |
| Power-on reset circuit Grant 6,744,291 - Payne , et al. June 1, 2 | 2004-06-01 |
| High speed zero DC power programmable logic device (PLD) architecture App 20040056679 - Pathak, Saroj ; et al. | 2004-03-25 |
| Power-on reset circuit App 20040041601 - Payne, James E. ; et al. | 2004-03-04 |
| High voltage bit/column latch for Vcc operation Grant 6,618,289 - Pathak , et al. September 9, 2 | 2003-09-09 |
| High voltage bit/column latch for Vcc operation App 20030081448 - Pathak, Saroj ; et al. | 2003-05-01 |
| Secure programmable logic device Grant 6,331,784 - Mason , et al. December 18, 2 | 2001-12-18 |
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