KUNG; David S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for KUNG; David S..The latest application filed is for "deep learning to correct map and image features".

Company Profile

3.18.20

KUNG; David S. - Chappaqua NY
Kung; David S. - Westchester NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Deep Learning To Correct Map And Image Features App 20210248765 - ZHANG; Rui ; et al.	2021-08-12
Multi-directional reduction in large scale deep-learning Grant 10,922,606 - Cho , et al. February 16, 2	2021-02-16
Margin Based Adversarial Computer Program App 20200226425 - Zhang; Yang ; et al.	2020-07-16
Large Model Support In Deep Learning App 20200143251 - Cho; Minsik ; et al.	2020-05-07
Multi-directional Reduction in Large Scale Deep-Learning App 20180357534 - Cho; Minsik ; et al.	2018-12-13
Performing automatic map reduce job optimization using a resource supply-demand based approach Grant 10,013,289 - Kung , et al. July 3, 2	2018-07-03
Performing Automatic Map Reduce Job Optimization Using A Resource Supply-demand Based Approach App 20170315848 - Kung; David S. ; et al.	2017-11-02
Enabling Statistical Testing Using Deterministic Multi-corner Timing Analysis App 20130283223 - Agrawal; Bhavna ; et al.	2013-10-24
Enabling statistical testing using deterministic multi-corner timing analysis Grant 8,560,994 - Agrawal , et al. October 15, 2	2013-10-15
Three dimensional integrated circuit and method of design Grant 7,723,207 - Alam , et al. May 25, 2	2010-05-25
Multiple Voltage Integrated Circuit And Design Method Therefor App 20090032903 - Correale, JR.; Anthony ; et al.	2009-02-05
Multiple voltage integrated circuit and design method therefor Grant 7,480,883 - Correale, Jr. , et al. January 20, 2	2009-01-20
Single supply level converter Grant 7,336,100 - Correale, Jr. , et al. February 26, 2	2008-02-26
Three Dimensional Integrated Circuit And Method Of Design App 20080042140 - Alam; Syed M. ; et al.	2008-02-21
Three dimensional integrated circuit Grant 7,312,487 - Alam , et al. December 25, 2	2007-12-25
Three Dimensional Integrated Circuit And Method Of Design App 20070287224 - Alam; Syed M. ; et al.	2007-12-13
Clock tree distribution generation by determining allowed placement regions for clocked elements Grant 7,225,421 - Migatz , et al. May 29, 2	2007-05-29
Method for performing timing closure on VLSI chips in a distributed environment Grant 7,178,120 - Hieter , et al. February 13, 2	2007-02-13
Multiple Voltage Integrated Circuit And Design Method Therefor App 20070028193 - Correale; Anthony JR. ; et al.	2007-02-01
Single Supply Level Converter App 20060279334 - Correale; Anthony JR. ; et al.	2006-12-14
Single supply level converter Grant 7,119,578 - Correale, Jr. , et al. October 10, 2	2006-10-10
Multiple voltage integrated circuit and design method therefor Grant 7,111,266 - Correale, Jr. , et al. September 19, 2	2006-09-19
Method Of Clock Tree Distribution Generation By Determining Allowed Placement Regions For Clocked Elements App 20060190899 - Migatz; William R. ; et al.	2006-08-24
Method and program product of level converter optimization Grant 7,089,510 - Correale, Jr. , et al. August 8, 2	2006-08-08
Integrated circuit logic with self compensating block delays Grant 7,084,476 - Gupta , et al. August 1, 2	2006-08-01
Three dimensional integrated circuit and method of design App 20060033110 - Alam; Syed M. ; et al.	2006-02-16
Integrated circuit logic with self compensating block delays App 20050189604 - Gupta, Puneet ; et al.	2005-09-01
Method and program product of level converter optimization App 20050114815 - Correale, Anthony JR. ; et al.	2005-05-26
Single supply level converter App 20050110519 - Correale, Anthony JR. ; et al.	2005-05-26
Multiple voltage integrated circuit and design method therefor App 20050114814 - Correale, Anthony JR. ; et al.	2005-05-26
Method for performing timing closure on VLSI chips in a distributed environment App 20040133860 - Hieter, Nathaniel ; et al.	2004-07-08
System and method for fast interconnect delay estimation through iterative refinement Grant 6,601,223 - Puri , et al. July 29, 2	2003-07-29
Timing-driven Global Placement Based On Geometry-aware Timing Budgets App 20030005398 - Cho, Jun-Dong ; et al.	2003-01-02
Timing-driven global placement based on geometry-aware timing budgets Grant 6,480,991 - Cho , et al. November 12, 2	2002-11-12
System and method for improving logic synthesis in logic circuits Grant 6,253,356 - Kung June 26, 2	2001-06-26
Method and apparatus for logic synthesis employing size independent timing optimization Grant 6,167,557 - Kudva , et al. December 26, 2	2000-12-26

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