Kundu; Sandip

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kundu; Sandip.The latest application filed is for "apparatus and method for detecting or repairing minimum delay errors".

Company Profile

0.11.9

Kundu; Sandip - Amherst MA
Kundu; Sandip - Austin TX
Kundu; Sandip - Cupertino CA
Kundu; Sandip - Mohegan Lake NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for detecting or repairing minimum delay errors Grant 9,520,877 - Meinerzhagen , et al. December 13, 2	2016-12-13
Apparatus And Method For Detecting Or Repairing Minimum Delay Errors App 20160173090 - Meinerzhagen; Pascal A. ; et al.	2016-06-16
Weight compression/decompression system Grant 7,197,721 - Patil , et al. March 27, 2	2007-03-27
Dft technique for avoiding contention/conflict in logic built-in self-test Grant 7,096,397 - Kundu , et al. August 22, 2	2006-08-22
Generalized fault model for defects and circuit marginalities Grant 7,036,063 - Kundu , et al. April 25, 2	2006-04-25
Testing integrated circuits using high bandwidth wireless technology App 20060052075 - Galivanche; Rajeshwar ; et al.	2006-03-09
Method and apparatus for modeling and circuits with asynchronous behavior Grant 6,973,422 - Yadavalli , et al. December 6, 2	2005-12-06
Scan design for double-edge-triggered flip-flops Grant 6,938,225 - Kundu August 30, 2	2005-08-30
Method and apparatus for power supply noise modeling and test pattern development Grant 6,912,701 - Kundu June 28, 2	2005-06-28
Generalized fault model for defects and circuit marginalities App 20040205436 - Kundu, Sandip ; et al.	2004-10-14
Weight compression/decompression system App 20040117710 - Patil, Srinivas ; et al.	2004-06-17
Method and apparatus for power supply noise modeling and test pattern development App 20040088615 - Kundu, Sandip	2004-05-06
Generalized fault model for defects and circuit marginalities App 20040064773 - Kundu, Sandip ; et al.	2004-04-01
System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation Grant 6,715,091 - Kundu March 30, 2	2004-03-30
Scan design for double-edge-triggered flip-flops App 20040041610 - Kundu, Sandip	2004-03-04
Simulation-based technique for contention avoidance in automatic test pattern generation App 20030188273 - Kundu, Sandip ; et al.	2003-10-02
Dft technique for avoiding contention/conflict in logic built-in self-test App 20030053358 - Kundu, Sandip ; et al.	2003-03-20
Constrained signature-based test Grant 6,510,398 - Kundu , et al. January 21, 2	2003-01-21
Technique for sorting high frequency integrated circuits Grant 5,796,751 - Kundu August 18, 1	1998-08-18
Adjustable weighted random test pattern generator for logic circuits Grant 5,297,151 - Gruetzner , et al. March 22, 1	1994-03-22

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