Patent | Date |
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Fast Matrix Multiplication App 20220012304 - Kumar; Sudarshan | 2022-01-13 |
Low Power Content Addressable Memory App 20220013154 - Kumar; Sudarshan | 2022-01-13 |
Low power content addressable memory Grant 11,017,858 - Kumar May 25, 2 | 2021-05-25 |
Low power and low cost projection system App 20120057135 - Kumar; Sudarshan | 2012-03-08 |
Method and apparatus to limit current-change induced voltage changes in a microcircuit Grant 7,685,451 - Burns , et al. March 23, 2 | 2010-03-23 |
Gate-clocked domino circuits with reduced leakage current Grant 6,952,118 - Jamshidi , et al. October 4, 2 | 2005-10-04 |
Single stage pulsed domino circuit for driving cascaded skewed static logic circuits Grant 6,833,735 - Kumar , et al. December 21, 2 | 2004-12-21 |
Method and apparatus for improving the performance of a floating point multiplier accumulator Grant 6,820,106 - Vijayrao , et al. November 16, 2 | 2004-11-16 |
Single stage pulsed domino circuit for driving cascaded skewed static logic circuits App 20040124882 - Kumar, Sudarshan ;   et al. | 2004-07-01 |
Gate-clocked domino circuits with reduced leakage current App 20040119503 - Jamshidi, Shahram ;   et al. | 2004-06-24 |
Method and apparatus to limit current-change induced voltage changes in a microcircuit App 20040120445 - Burns, James S. ;   et al. | 2004-06-24 |
Low power entry latch to interface static logic with dynamic logic Grant 6,707,318 - Kumar , et al. March 16, 2 | 2004-03-16 |
Low power precharge scheme for memory bit lines Grant 6,631,093 - Kumar , et al. October 7, 2 | 2003-10-07 |
Low power entry latch to interface static logic with dynamic logic App 20030184344 - Kumar, Sudarshan ;   et al. | 2003-10-02 |
Multi-entry register cell Grant 6,628,539 - Kumar , et al. September 30, 2 | 2003-09-30 |
Method and apparatus for low power memory bit line precharge Grant 6,629,194 - Kumar , et al. September 30, 2 | 2003-09-30 |
Method and apparatus for low power domino decoding App 20030025531 - Kumar, Sudarshan ;   et al. | 2003-02-06 |
Low Power Precharge Scheme For Memory Bit Lines App 20030002382 - Kumar, Sudarshan ;   et al. | 2003-01-02 |
Method and apparatus for low power memory bit line precharge App 20020184431 - Kumar, Sudarshan ;   et al. | 2002-12-05 |
Multi-entry register cell App 20020181268 - Kumar, Sudarshan ;   et al. | 2002-12-05 |
Method and apparatus for reducing soft errors in dynamic circuits Grant 6,351,151 - Kumar , et al. February 26, 2 | 2002-02-26 |
Method and apparatus for reducing soft errors in dynamic circuits App 20010040467 - Kumar, Sudarshan ;   et al. | 2001-11-15 |
Low power multiplexer with shared, clocked transistor Grant 6,111,435 - Lan , et al. August 29, 2 | 2000-08-29 |
Method for verifying hold time in integrated circuit design Grant 6,023,767 - Kumar , et al. February 8, 2 | 2000-02-08 |
Method and apparatus for providing a high speed tristate buffer Grant 5,900,744 - Bisen , et al. May 4, 1 | 1999-05-04 |
Positive feedback circuit for fast domino logic Grant 5,661,675 - Chin , et al. August 26, 1 | 1997-08-26 |
MOS adder with minimum pass gates in carry line Grant 4,905,180 - Kumar February 27, 1 | 1990-02-27 |