Kuhn; Justus

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kuhn; Justus.The latest application filed is for "self test for the phase angle of the data read clock signal dqs".

Company Profile

0.18.19

Kuhn; Justus - Munchen DE
Kuhn; Justus - Munich DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self test for the phase angle of the data read clock signal DQS Grant 7,307,895 - Kuhn , et al. December 11, 2	2007-12-11
Method and device for generating digital signal patterns Grant 7,117,403 - Ernst , et al. October 3, 2	2006-10-03
Test circuit for testing a synchronous memory circuit Grant 7,117,404 - Ernst , et al. October 3, 2	2006-10-03
System for testing fast synchronous digital circuits, particularly semiconductor memory chips Grant 7,062,690 - Ernst , et al. June 13, 2	2006-06-13
Method and apparatus for synchronous signal transmission between at least two logic or memory components Grant 7,043,653 - Kuhn , et al. May 9, 2	2006-05-09
Self test for the phase angle of the data read clock signal DQS App 20060064620 - Kuhn; Justus ; et al.	2006-03-23
Address generator for generating addresses for testing a circuit Grant 6,957,373 - Ernst , et al. October 18, 2	2005-10-18
Method of matching different signal propagation times between a controller and at least two processing units, and a computer system Grant 6,954,871 - Kuhn October 11, 2	2005-10-11
Device and method for reducing the number of addresses of faulty memory cells Grant 6,910,161 - Kuhn , et al. June 21, 2	2005-06-21
Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested Grant 6,871,306 - Ernst , et al. March 22, 2	2005-03-22
Test data generator Grant 6,865,707 - Ernst , et al. March 8, 2	2005-03-08
Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices Grant 6,862,702 - Ernst , et al. March 1, 2	2005-03-01
Method and probe card configuration for testing a plurality of integrated circuits in parallel Grant 6,853,206 - Hubner , et al. February 8, 2	2005-02-08
Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits Grant 6,839,397 - Ernst , et al. January 4, 2	2005-01-04
Test configuration and test method for testing a plurality of integrated circuits in parallel Grant 6,762,611 - Hubner , et al. July 13, 2	2004-07-13
Method and probe card configuration for testing a plurality of integrated circuits in parallel App 20040124863 - Hubner, Michael ; et al.	2004-07-01
Test circuit Grant 6,744,272 - Ernst , et al. June 1, 2	2004-06-01
System for testing fast integrated digital circuits, in particular semiconductor memory modules Grant 6,721,904 - Ernst , et al. April 13, 2	2004-04-13
Test circuit for testing a circuit Grant 6,618,305 - Ernst , et al. September 9, 2	2003-09-09
System for testing fast synchronous semiconductor circuits Grant 6,556,492 - Ernst , et al. April 29, 2	2003-04-29
Method and apparatus for synchronous signal transmission between at least two logic/memory components App 20030033551 - Kuhn, Justus ; et al.	2003-02-13
Test circuit for testing a synchronous memory circuit App 20030005361 - Ernst, Wolfgang ; et al.	2003-01-02
Test circuit for testing a synchronous circuit App 20030005389 - Ernst, Wolfgang ; et al.	2003-01-02
Test circuit for testing a circuit App 20020196688 - Ernst, Wolfgang ; et al.	2002-12-26
Test circuit App 20020171447 - Ernst, Wolfgang ; et al.	2002-11-21
Method of matching different signal propagation times between a controller and at least two processing units, and a computer system App 20020174313 - Kuhn, Justus	2002-11-21
Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested App 20020160558 - Ernst, Wolfgang ; et al.	2002-10-31
Test data generator App 20020157052 - Ernst, Wolfgang ; et al.	2002-10-24
Test configuration and test method for testing a plurality of integrated circuits in parallel App 20020089341 - Hubner, Michael ; et al.	2002-07-11
Device and method for reducing the number of addresses of faulty memory cells App 20020087926 - Kuhn, Justus ; et al.	2002-07-04
System for testing fast synchronous digital circuits, particularly semiconductor memory chips App 20020070748 - Ernst, Wolfgang ; et al.	2002-06-13
Field-effect-controlled transistor and method for fabricating the transistor App 20020014669 - Widmann, Dietrich ; et al.	2002-02-07
System for testing fast synchronous semiconductor circuits App 20020012283 - Ernst, Wolfgang ; et al.	2002-01-31
Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices App 20020012286 - Ernst, Wolfgang ; et al.	2002-01-31
Method and device for generating digital signal patterns App 20020009007 - Ernst, Wolfgang ; et al.	2002-01-24
Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits App 20020010878 - Ernst, Wolfgang ; et al.	2002-01-24
System for testing fast integrated digital circuits, in particular semiconductor memory modules App 20020010877 - Ernst, Wolfgang ; et al.	2002-01-24

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