| Patent | Date |
|---|
Software and hardware emulation system
Grant 10,713,069 - Boshernitsan , et al. | 2020-07-14 |
Static analysis of computer code to determine impact of change to a code component upon a dependent code component
Grant 9,836,390 - Boshernitsan , et al. December 5, 2 | 2017-12-05 |
Prioritization of tests of computer program code
Grant 9,612,943 - Boshernitsan , et al. April 4, 2 | 2017-04-04 |
Software and Hardware Emulation System
App 20170017506 - Boshernitsan; Marat ; et al. | 2017-01-19 |
Policy evaluation based upon dynamic observation, static analysis and code change history
Grant 9,317,399 - Boshernitsan , et al. April 19, 2 | 2016-04-19 |
Static Analysis Of Computer Code To Determine Impact Of Change To A Code Component Upon A Dependent Code Component
App 20150317236 - Boshernitsan; Marat ; et al. | 2015-11-05 |
Static analysis of computer code to determine impact of change to a code component upon a dependent code component
Grant 9,032,376 - Boshernitsan , et al. May 12, 2 | 2015-05-12 |
Prioritization Of Tests Of Computer Program Code
App 20150007140 - Boshernitsan; Marat ; et al. | 2015-01-01 |
General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software
Grant 8,862,439 - Kuehlmann , et al. October 14, 2 | 2014-10-14 |
Static Analysis Of Computer Code To Determine Impact Of Change To A Code Component Upon A Dependent Code Component
App 20140130020 - Boshernitsan; Marat ; et al. | 2014-05-08 |
Policy Evaluation Based Upon Dynmamic Observation, Static Analysis And Code Change History
App 20140096113 - Kuehlmann; Andreas ; et al. | 2014-04-03 |
Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software
Grant 8,656,330 - Kuehlmann , et al. February 18, 2 | 2014-02-18 |
Optimizing integrated circuit design through use of sequential timing information
Grant 8,589,845 - Albrecht , et al. November 19, 2 | 2013-11-19 |
Temporal decomposition for design and verification
Grant 8,418,101 - Kuehlmann , et al. April 9, 2 | 2013-04-09 |
Temporal decomposition for design and verification
Grant 8,413,090 - Kuehlmann , et al. April 2, 2 | 2013-04-02 |
Reducing critical cycle delay in an integrated circuit design through use of sequential slack
Grant 8,307,316 - Albrecht , et al. November 6, 2 | 2012-11-06 |
Reducing Critical Cycle Delay In An Integrated Circuit Design Through Use Of Sequential Slack
App 20110252389 - ALBRECHT; Christoph ; et al. | 2011-10-13 |
System, methods and apparatus for generation of simulation stimulus
Grant 8,020,125 - Kuehlmann , et al. September 13, 2 | 2011-09-13 |
Reducing critical cycle delay in an integrated circuit design through use of sequential slack
Grant 7,913,210 - Albrecht , et al. March 22, 2 | 2011-03-22 |
Temporal decomposition for design and verification
Grant 7,900,173 - Kuehlmann , et al. March 1, 2 | 2011-03-01 |
Optimizing integrated circuit design through use of sequential timing information
Grant 7,743,354 - Albrecht , et al. June 22, 2 | 2010-06-22 |
Optimizing Integrated Circuit Design Through Use Of Sequential Timing Information
App 20100115477 - ALBRECHT; Christoph ; et al. | 2010-05-06 |
Data path and placement optimization in an integrated circuit through use of sequential timing information
Grant 7,624,364 - Albrecht , et al. November 24, 2 | 2009-11-24 |
Temporal decomposition for design and verification
Grant 7,596,770 - Kuehlmann , et al. September 29, 2 | 2009-09-29 |
Optimization of combinational logic synthesis through clock latency scheduling
Grant 7,559,040 - Albrecht , et al. July 7, 2 | 2009-07-07 |
Optimizing integrated circuit design through use of sequential timing information
App 20080276210 - ALBRECHT; Christoph ; et al. | 2008-11-06 |
Optimizing Integrated Circuit Design Through Use Of Sequential Timing Information
App 20080276208 - Albrecht; Christoph ; et al. | 2008-11-06 |
Optimizing integrated circuit design through use of sequential timing information
App 20080276209 - ALBRECHT; Christoph ; et al. | 2008-11-06 |
Multi-domain clock skew scheduling
Grant 7,296,246 - Kuehlmann , et al. November 13, 2 | 2007-11-13 |
Framework for multiple-engine based verification tools for integrated circuits
Grant 6,698,003 - Baumgartner , et al. February 24, 2 | 2004-02-24 |
Framework for multiple-engine based verification tools for integrated circuits
App 20030110455 - Baumgartner, Jason Raymond ; et al. | 2003-06-12 |
Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis
Grant 6,473,884 - Ganai , et al. October 29, 2 | 2002-10-29 |
Method for performing functional comparison of combinational circuits
Grant 6,035,107 - Kuehlmann , et al. March 7, 2 | 2000-03-07 |
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