| Patent | Date |
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Hardware execution driven application level derating calculation for soft error rate analysis
Grant 8,949,101 - Bose , et al. February 3, 2 | 2015-02-03 |
Tunable error resilience computing
Grant 8,832,707 - Henderson , et al. September 9, 2 | 2014-09-09 |
Method and system for controlling power in a chip through a power performance monitor and control unit
Grant 8,639,955 - Bose , et al. January 28, 2 | 2014-01-28 |
Hardware Execution Driven Application Level Derating Calculation for Soft Error Rate Analysis
App 20130096902 - Bose; Pradip ; et al. | 2013-04-18 |
Method And System For Controlling Power In A Chip Through A Power-performance Monitor And Control Unit
App 20120054528 - BOSE; PRADIP ; et al. | 2012-03-01 |
Method and system for controlling power in a chip through a power-performance monitor and control unit
Grant 8,112,642 - Bose , et al. February 7, 2 | 2012-02-07 |
Modeling system-level effects of soft errors
Grant 8,091,050 - Bose , et al. January 3, 2 | 2012-01-03 |
Tunable Error Resilience Computing
App 20110154351 - Henderson; Daniel J. ; et al. | 2011-06-23 |
Method and system of peak power enforcement via autonomous token-based control and management
Grant 7,930,578 - Bose , et al. April 19, 2 | 2011-04-19 |
Method for constructing autonomic advisors and learning procedural knowledge from scored examples
Grant 7,801,835 - Bergman , et al. September 21, 2 | 2010-09-21 |
Three dimensional integrated circuit and method of design
Grant 7,723,207 - Alam , et al. May 25, 2 | 2010-05-25 |
Modeling System-Level Effects of Soft Errors
App 20100083203 - Bose; Pradip ; et al. | 2010-04-01 |
Interlocked synchronous pipeline clock gating
Grant 7,685,457 - Jacobson , et al. March 23, 2 | 2010-03-23 |
Logic block timing estimation using conesize
Grant 7,676,779 - Bergamaschi , et al. March 9, 2 | 2010-03-09 |
Method And System Of Peak Power Enforcement Via Autonomous Token-based Control And Management
App 20090089602 - Bose; Pradip ; et al. | 2009-04-02 |
System to Identify Timing Differences from Logic Block Changes and Associated Methods
App 20090070720 - Bergamaschi; Reinaldo A. ; et al. | 2009-03-12 |
Logic Block Timing Estimation Using Conesize
App 20090070719 - Bergamaschi; Reinaldo A. ; et al. | 2009-03-12 |
Method And System For Controlling Power In A Chip Through A Power-performance Monitor And Control Unit
App 20090049318 - Bose; Pradip ; et al. | 2009-02-19 |
Method of stalling one or more stages in an interlocked synchronous pipeline
Grant 7,475,227 - Jacobson , et al. January 6, 2 | 2009-01-06 |
Method and system for controlling power in a chip through a power-performance monitor and control unit
Grant 7,421,601 - Bose , et al. September 2, 2 | 2008-09-02 |
Method For Optimization Of Logic Circuits For Routability Improvement
App 20080195984 - Dougherty,; William E. ; et al. | 2008-08-14 |
Method for optimization of logic circuits for routability
Grant 7,373,615 - Dougherty, Jr. , et al. May 13, 2 | 2008-05-13 |
Three Dimensional Integrated Circuit And Method Of Design
App 20080042140 - Alam; Syed M. ; et al. | 2008-02-21 |
Three dimensional integrated circuit
Grant 7,312,487 - Alam , et al. December 25, 2 | 2007-12-25 |
Interlocked Synchronous Pipeline Clock Gating
App 20070294548 - JACOBSON; Hans M. ; et al. | 2007-12-20 |
Three Dimensional Integrated Circuit And Method Of Design
App 20070287224 - Alam; Syed M. ; et al. | 2007-12-13 |
Interlocked synchronous pipeline clock gating
Grant 7,308,593 - Jacobson , et al. December 11, 2 | 2007-12-11 |
Method and system for controlling power in a chip through a power-performance monitor and control unit
App 20070198863 - Bose; Pradip ; et al. | 2007-08-23 |
Method for constructing autonomic advisors and learning procedural knowledge from scored examples
App 20070005539 - Bergman; Lawrence ; et al. | 2007-01-04 |
System and method for topology selection to minimize leakage power during synthesis
Grant 7,100,144 - Jacobson , et al. August 29, 2 | 2006-08-29 |
Interlocked synchronous pipeline clock gating
App 20060161795 - Jacobson; Hans M. ; et al. | 2006-07-20 |
Interlocked synchronous pipeline clock gating
App 20060156046 - Jacobson; Hans M. ; et al. | 2006-07-13 |
Processor with demand-driven clock throttling power reduction
Grant 7,076,681 - Bose , et al. July 11, 2 | 2006-07-11 |
Interlocked synchronous pipeline clock gating
Grant 7,065,665 - Jacobson , et al. June 20, 2 | 2006-06-20 |
Three dimensional integrated circuit and method of design
App 20060033110 - Alam; Syed M. ; et al. | 2006-02-16 |
Method and structure for short range leakage control in pipelined circuits
Grant 6,946,869 - Jacobson , et al. September 20, 2 | 2005-09-20 |
Method for optimization of logic circuits for routability
App 20050183046 - Dougherty, William E. JR. ; et al. | 2005-08-18 |
System and method for topology selection to minimize leakage power during synthesis
App 20050125761 - Jacobson, Hans M. ; et al. | 2005-06-09 |
Method and structure for short range leakage control in pipelined circuits
App 20050083081 - Jacobson, Hans M. ; et al. | 2005-04-21 |
Interlocked synchronous pipeline clock gating
App 20040068640 - Jacobson, Hans M. ; et al. | 2004-04-08 |
Processor with demand-driven clock throttling power reduction
App 20040044915 - Bose, Pradip ; et al. | 2004-03-04 |
Low-power circuit structures and methods for content addressable memories and random access memories
Grant 6,608,771 - Jacobson , et al. August 19, 2 | 2003-08-19 |
Low-power Circuit Structures And Methods For Content Addressable Memories And Random Access Memories
App 20030043665 - Jacobson, Hans M. ; et al. | 2003-03-06 |
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