Kudo; Mamoru
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kudo; Mamoru.The latest application filed is for "semiconductor device".
- Kudo; Mamoru - Kanagawa JP
| Patent | Date |
|---|---|
| Phase error determination method and digital phase-locked loop system Grant 7,730,366 - Nakamura , et al. June 1, 2 | 2010-06-01 |
| Semiconductor device Grant 7,578,676 - Sukegawa , et al. August 25, 2 | 2009-08-25 |
| Semiconductor device Grant 7,554,186 - Kudo , et al. June 30, 2 | 2009-06-30 |
| Semiconductor Device App 20080315386 - KUDO; Mamoru ; et al. | 2008-12-25 |
| Phase error determination method and digital phase-locked loop system Grant 7,469,367 - Nakamura , et al. December 23, 2 | 2008-12-23 |
| Semiconductor Device App 20080188096 - SUKEGAWA; Shunichi ; et al. | 2008-08-07 |
| Semiconductor device Grant 7,351,068 - Sukegawa , et al. April 1, 2 | 2008-04-01 |
| Digital PLL device Grant 7,342,986 - Nakamura , et al. March 11, 2 | 2008-03-11 |
| Phase error determination method and digital phase-locked loop system Grant 7,315,968 - Nakamura , et al. January 1, 2 | 2008-01-01 |
| Semiconductor Device App 20070184677 - SUKEGAWA; Shunichi ; et al. | 2007-08-09 |
| Phase error determination method and digital phase-locked loop system App 20070094549 - Nakamura; Shinobu ; et al. | 2007-04-26 |
| Phase error determination method and digital phase-locked loop system App 20070088992 - Nakamura; Shinobu ; et al. | 2007-04-19 |
| Recorder, recording method, reproducer, reproducing method, and recording medium App 20060098541 - Kudo; Mamoru | 2006-05-11 |
| Phase-locked loop circuit for reproducing a channel clock Grant 6,992,958 - Kudo , et al. January 31, 2 | 2006-01-31 |
| Phase error determination method and digital phase-locked loop system App 20050022076 - Nakamura, Shinobu ; et al. | 2005-01-27 |
| Digital PLL device App 20040264623 - Nakamura, Shinobu ; et al. | 2004-12-30 |
| Phase-locked loop circuit App 20020105365 - Kudo, Mamoru ; et al. | 2002-08-08 |
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