Kuan; Hsin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kuan; Hsin.The latest application filed is for "chip package and manufacturing method thereof".

Company Profile

3.7.8

Kuan; Hsin - Zhubei TW
KUAN; Hsin - Zhubei City TW
Kuan; Hsin - Jhongli TW
Kuan; Hsin - Jhongli City TW
Kuan; Hsin - Hsinchu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Chip package and manufacturing method thereof Grant 10,714,528 - Kuan , et al.	2020-07-14
Chip package and manufacturing method thereof Grant 10,347,616 - Kuan , et al. July 9, 2	2019-07-09
Chip Package And Manufacturing Method Thereof App 20190140012 - KUAN; Hsin ; et al.	2019-05-09
Chip package and method for forming the same Grant 10,109,663 - Huang , et al. October 23, 2	2018-10-23
Chip Package And Manufacturing Method Thereof App 20170330871 - KUAN; Hsin ; et al.	2017-11-16
Passive component structure and manufacturing method thereof Grant 9,761,555 - Lai , et al. September 12, 2	2017-09-12
Chip Package And Method For Forming The Same App 20170092607 - KUAN; Hsin ; et al.	2017-03-30
Chip Package And Method For Forming The Same App 20170077158 - HUANG; Yu-Lung ; et al.	2017-03-16
Semiconductor stack structure and fabrication method thereof Grant 9,177,862 - Ho , et al. November 3, 2	2015-11-03
Passive Component Structure And Manufacturing Method Thereof App 20150214162 - LAI; Jiun-Yen ; et al.	2015-07-30
Semiconductor Stack Structure And Fabrication Method Thereof App 20130168868 - Ho; Yeh-Shih ; et al.	2013-07-04
Method for bin-based control Grant 8,041,451 - Wu , et al. October 18, 2	2011-10-18
Method For Bin-based Control App 20100268367 - Wu; Sunny ; et al.	2010-10-21
High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage Grant 7,301,185 - Chen , et al. November 27, 2	2007-11-27
High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage App 20060113627 - Chen; Chung-I ; et al.	2006-06-01

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.