loadpatents
name:-0.028255224227905
name:-0.027729034423828
name:-0.0012209415435791
Ku; Victor Patent Filings

Ku; Victor

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ku; Victor.The latest application filed is for "methods for fabricating dual material gate in a semiconductor device".

Company Profile
0.22.17
  • Ku; Victor - Yorktown Heights NY
  • Ku; Victor - Tarrytown NY
  • Ku; Victor - Westboro MA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Camera
Grant D930,729 - Ou , et al. September 14, 2
2021-09-14
Handheld inspection device
Grant D891,946 - Song , et al.
2020-08-04
Handheld sensor device
Grant D891,947 - Song , et al.
2020-08-04
Handheld meter
Grant D891,958 - Song , et al.
2020-08-04
Handheld sensor device
Grant D890,000 - Song , et al.
2020-07-14
CMOS silicide metal gate integration
Grant 7,655,557 - Amos , et al. February 2, 2
2010-02-02
Methods for fabricating dual material gate in a semiconductor device
Grant 7,635,648 - Peidous , et al. December 22, 2
2009-12-22
Methods For Fabricating Dual Material Gate In A Semiconductor Device
App 20090258484 - PEIDOUS; IGOR ;   et al.
2009-10-15
Cmos Silicide Metal Gate Integration
App 20080254622 - Amos; Ricky S. ;   et al.
2008-10-16
CMOS silicide metal gate integration
Grant 7,411,227 - Amos , et al. August 12, 2
2008-08-12
Process options of forming silicided metal gates for advanced CMOS devices
Grant 7,326,610 - Amos , et al. February 5, 2
2008-02-05
Semiconductor devices and methods of manufacture thereof
App 20070134861 - Han; Jin-Ping ;   et al.
2007-06-14
CMOS silicide metal gate integration
App 20060189061 - Amos; Ricky S. ;   et al.
2006-08-24
CMOS silicide metal gate integration
Grant 7,056,782 - Amos , et al. June 6, 2
2006-06-06
FET gate structure with metal gate electrode and silicide contact
Grant 7,056,794 - Ku , et al. June 6, 2
2006-06-06
Process options of forming silicided metal gates for advanced CMOS devices
App 20060105515 - Amos; Ricky S. ;   et al.
2006-05-18
Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS
Grant 7,041,538 - Ieong , et al. May 9, 2
2006-05-09
Process options of forming silicided metal gates for advanced CMOS devices
Grant 7,029,966 - Amos , et al. April 18, 2
2006-04-18
Method of forming FET silicide gate structures incorporating inner spacers
Grant 6,974,736 - Ku , et al. December 13, 2
2005-12-13
CMOS silicide metal gate integration
App 20050186747 - Amos, Ricky S. ;   et al.
2005-08-25
Method for integration of silicide contacts and silicide gate metals
Grant 6,927,117 - Cabral, Jr. , et al. August 9, 2
2005-08-09
Method for forming metal replacement gate of high performance
Grant 6,921,711 - Cabral, Jr. , et al. July 26, 2
2005-07-26
Method Of Forming Fet Silicide Gate Structures Incorporating Inner Spacers
App 20050153494 - Ku, Victor ;   et al.
2005-07-14
Fet Gate Structure With Metal Gate Electrode And Silicide Contact
App 20050153530 - Ku, Victor ;   et al.
2005-07-14
Method for integration of silicide contacts and silicide gate metals
App 20050118757 - Cabral, Cyril JR. ;   et al.
2005-06-02
Process Options Of Forming Silicided Metal Gates For Advanced Cmos Devices
App 20050064690 - Amos, Ricky S. ;   et al.
2005-03-24
Structure And Method For Metal Replacement Gate Of High Performance
App 20050051854 - Cabral, Cyril JR. ;   et al.
2005-03-10
Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
App 20040104433 - Ieong, Meikei ;   et al.
2004-06-03
Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
Grant 6,677,646 - Ieong , et al. January 13, 2
2004-01-13
Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
App 20030189228 - Ieong, Meikei ;   et al.
2003-10-09
Method for forming junction on insulator (JOI) structure
Grant 6,544,874 - Mandelman , et al. April 8, 2
2003-04-08
Method For Forming Junction On Insulator (joi) Structure
App 20030032272 - Mandelman, Jack A. ;   et al.
2003-02-13
Method for forming notch gate having self-aligned raised source/drain structure
Grant 6,506,649 - Fung , et al. January 14, 2
2003-01-14
Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
App 20020132394 - Ku, Victor ;   et al.
2002-09-19
Method For Forming Notch Gate Having Self-aligned Raised Source/drain Structure
App 20020132431 - Fung, Ka Hing ;   et al.
2002-09-19
Low Dielectric Constant Sidewall Spacer Using Notch Gate Process
App 20020096695 - Ajmera, Atul C. ;   et al.
2002-07-25
Secondary storage facility for data processing systems
Grant 3,999,163 - Levy , et al. December 21, 1
1976-12-21
Drive condition detecting circuit for secondary storage facilities in data processing systems
Grant 3,911,400 - Levy , et al. October 7, 1
1975-10-07
Diagnostic circuit for data processing system
Grant 3,911,402 - McLean , et al. October 7, 1
1975-10-07

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