| Patent | Date |
|---|
Integrated circuit device and method of manufacturing the same
Grant 10,651,179 - Park , et al. | 2020-05-12 |
Semiconductor device including contact plug and method of manufacturing the same
Grant 10,134,856 - Eom , et al. November 20, 2 | 2018-11-20 |
Integrated Circuit Device And Method Of Manufacturing The Same
App 20180277547 - PARK; Hong-bae ; et al. | 2018-09-27 |
Integrated circuit device and method of manufacturing the same
Grant 10,014,304 - Park , et al. July 3, 2 | 2018-07-03 |
Method of calibrating target values and processing systems configured to calibrate the target values
Grant 9,613,002 - Han , et al. April 4, 2 | 2017-04-04 |
Semiconductor Device Including Contact Plug And Method Of Manufacturing The Same
App 20170077248 - EOM; Da-Il ; et al. | 2017-03-16 |
Integrated Circuit Device And Method Of Manufacturing The Same
App 20170040328 - PARK; Hong-bae ; et al. | 2017-02-09 |
Integrated circuit device and method of manufacturing the same
Grant 9,508,727 - Park , et al. November 29, 2 | 2016-11-29 |
Integrated Circuit Device And Method Of Manufacturing The Same
App 20160133632 - PARK; Hong-bae ; et al. | 2016-05-12 |
Method of Calibrating Target Values and Processing Systems Configured to Calibrate the Target Values
App 20140229134 - Han; Chang-Ho ; et al. | 2014-08-14 |
Gate Oxide Film Including A Nitride Layer Deposited Thereon And Method Of Forming The Gate Oxide Film
App 20120241874 - KIM; BYUNG-DONG ; et al. | 2012-09-27 |
Method and apparatus for manufacturing a semiconductor
Grant 8,016,941 - Hierlemann , et al. September 13, 2 | 2011-09-13 |
Method for fabricating semiconductor device using a nickel salicide process
Grant 8,008,177 - San , et al. August 30, 2 | 2011-08-30 |
Methods For Forming Self-aligned Dual Stress Liners For Cmos Semiconductor Devices
App 20110163387 - Lee; Kyoung Woo ; et al. | 2011-07-07 |
Methods for forming self-aligned dual stress liners for CMOS semiconductor devices
Grant 7,911,001 - Lee , et al. March 22, 2 | 2011-03-22 |
Methods for forming contacts for dual stress liner CMOS semiconductor devices
Grant 7,816,271 - Lee , et al. October 19, 2 | 2010-10-19 |
CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein
Grant 7,800,134 - Lee , et al. September 21, 2 | 2010-09-21 |
Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes
Grant 7,790,622 - Lee , et al. September 7, 2 | 2010-09-07 |
Nickel alloy salicide transistor structure and method for manufacturing same
Grant 7,781,322 - Ku , et al. August 24, 2 | 2010-08-24 |
Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities
Grant 7,781,276 - Lee , et al. August 24, 2 | 2010-08-24 |
Methods of fabricating semiconductor device having a metal gate pattern
Grant 7,772,643 - Ku , et al. August 10, 2 | 2010-08-10 |
HDP/PECVD methods of fabricating stress nitride structures for field effect transistors
Grant 7,615,432 - Kim , et al. November 10, 2 | 2009-11-10 |
Methods of fabricating semiconductor device having a metal gate pattern
App 20090250752 - Ku; Ja-Hum ; et al. | 2009-10-08 |
Silicided polysilicon spacer for enhanced contact area
Grant 7,598,572 - Dyer , et al. October 6, 2 | 2009-10-06 |
Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface
Grant 7,586,175 - Lee , et al. September 8, 2 | 2009-09-08 |
Devices and methods for constructing electrically programmable integrated fuses for low power applications
Grant 7,576,407 - Ko , et al. August 18, 2 | 2009-08-18 |
CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein
App 20090194817 - Lee; Kyoung-woo ; et al. | 2009-08-06 |
Methods of fabricating a semiconductor device having a metal gate pattern
Grant 7,544,996 - Ku , et al. June 9, 2 | 2009-06-09 |
Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques
Grant 7,541,288 - Kim , et al. June 2, 2 | 2009-06-02 |
Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
Grant 7,534,678 - Lee , et al. May 19, 2 | 2009-05-19 |
Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities
App 20090124093 - Lee; Kyoung-woo ; et al. | 2009-05-14 |
Methods for forming damascene wiring structures having line and plug conductors formed from different materials
Grant 7,514,354 - Park , et al. April 7, 2 | 2009-04-07 |
Test structure of semiconductor device
Grant 7,501,651 - Sun , et al. March 10, 2 | 2009-03-10 |
Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes
App 20090017625 - Lee; Kyoung Woo ; et al. | 2009-01-15 |
Methods For Forming Self-Aligned Dual Stress Liners For CMOS Semiconductor Devices
App 20090014808 - Lee; Kyoung-Woo ; et al. | 2009-01-15 |
Methods For Forming Contacts For Dual Stress Liner CMOS Semiconductor Devices
App 20090017630 - Lee; Kyoung Woo ; et al. | 2009-01-15 |
Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer
Grant 7,465,617 - Ku , et al. December 16, 2 | 2008-12-16 |
Methods of forming integrated circuit devices having metal interconnect structures therein
Grant 7,435,673 - Lee , et al. October 14, 2 | 2008-10-14 |
Methods of Forming CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein and Circuits Formed Thereby
App 20080242015 - Lee; Kyoung-woo ; et al. | 2008-10-02 |
Methods of Forming Integrated Circuit Structures Using Insulator Deposition and Insulator Gap Filling Techniques
App 20080220584 - Kim; Jun-jung ; et al. | 2008-09-11 |
Method and Apparatus For Manufacturing A Semiconductor
App 20080188046 - Hierlemann; Matthias ; et al. | 2008-08-07 |
Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques
App 20080124859 - Sun; Min Chul ; et al. | 2008-05-29 |
CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same
App 20080116521 - Lee; Kyoung-woo ; et al. | 2008-05-22 |
Silicided Polysilicon Spacer For Enhanced Contact Area
App 20080102612 - Dyer; Thomas W. ; et al. | 2008-05-01 |
Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
Grant 7,365,025 - Lee , et al. April 29, 2 | 2008-04-29 |
Semiconductor Wafer Having Embedded Electroplating Current Paths To Provide Uniform Plating Over Wafer Surface
App 20080093746 - Lee; Kyoung Woo ; et al. | 2008-04-24 |
Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress Liner
App 20080029823 - Park; Jae-Eon ; et al. | 2008-02-07 |
Test structure of semiconductor device
Grant 7,317,204 - Sun , et al. January 8, 2 | 2008-01-08 |
Methods of fabricating a semiconductor device having a metal gate pattern
Grant 7,306,996 - Ku , et al. December 11, 2 | 2007-12-11 |
Methods of fabricating semiconductor devices having a dual stress liner
Grant 7,297,584 - Park , et al. November 20, 2 | 2007-11-20 |
Devices and methods for constructing electrically programmable integrated fuses for low power applications
App 20070252237 - Ko; Young-Gun ; et al. | 2007-11-01 |
Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
App 20070184649 - Lee; Kyoung-Woo ; et al. | 2007-08-09 |
Methods for forming damascene wiring structures having line and plug conductors formed from different materials
App 20070155165 - Park; Ki-Chul ; et al. | 2007-07-05 |
Nickel salicide process with reduced dopant deactivation
Grant 7,232,756 - Ku , et al. June 19, 2 | 2007-06-19 |
HDP/PECVD methods of fabricating stress nitride structures for field effect transistors, and field effect transistors so fabricated
App 20070096220 - Kim; Junjung ; et al. | 2007-05-03 |
Semiconductor device having a dual stress liner, method of manufacturing the semiconductor device and light exposure apparatus for forming the dual stress liner
App 20070082439 - Park; Jae-Eon ; et al. | 2007-04-12 |
Methods of forming integrated circuit devices having metal interconnect structures therein
App 20070072406 - Lee; Kyoung Woo ; et al. | 2007-03-29 |
Methods of fabricating a semiconductor device having a metal gate pattern
App 20060270205 - Ku; Ja-Hum ; et al. | 2006-11-30 |
Methods of fabricating a semiconductor device having a metal gate pattern
App 20060270204 - Ku; Ja-Hum ; et al. | 2006-11-30 |
Structure for measuring gate misalignment and measuring method thereof
App 20060231906 - Ko; Young-gun ; et al. | 2006-10-19 |
Semiconductor device having self-aligned silicide layer and method thereof
App 20060223296 - Sun; Min-Chul ; et al. | 2006-10-05 |
Methods of fabricating a semiconductor device having a metal gate pattern
Grant 7,109,104 - Ku , et al. September 19, 2 | 2006-09-19 |
Methods of forming a semiconductor device having a metal gate electrode and associated devices
Grant 7,098,123 - Heo , et al. August 29, 2 | 2006-08-29 |
Methods of fabricating a semiconductor device having MOS transistor with strained channel
Grant 7,084,061 - Sun , et al. August 1, 2 | 2006-08-01 |
Methods of forming a semiconductor device having a metal gate electrode and associated devices
App 20060163677 - Heo; Seong-Jun ; et al. | 2006-07-27 |
Test structure of semiconductor device
App 20060113534 - Sun; Min-chul ; et al. | 2006-06-01 |
Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer
App 20060057807 - Ku; Ja-Hum ; et al. | 2006-03-16 |
Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer
Grant 7,005,367 - Ku , et al. February 28, 2 | 2006-02-28 |
Salicide process using bi-metal layer and method of fabricating semiconductor device using the same
App 20060003534 - Roh; Kwan-Jong ; et al. | 2006-01-05 |
Method of forming a metal gate
Grant 6,960,515 - Cho , et al. November 1, 2 | 2005-11-01 |
Nickel alloy salicide transistor structure and method for manufacturing same
App 20050236715 - Ku, Ja-Hum ; et al. | 2005-10-27 |
Method of forming metal silicide film and method of manufacturing semiconductor device having metal silicide film
App 20050196960 - Koo, Kyeong-Mo ; et al. | 2005-09-08 |
Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film
Grant 6,936,528 - Koo , et al. August 30, 2 | 2005-08-30 |
Nickel salicide processes and methods of fabricating semiconductor devices using the same
App 20050158996 - Kim, Min-Joo ; et al. | 2005-07-21 |
Methods of fabricating integrated circuit gates by pretreating prior to oxidizing
Grant 6,864,132 - Cho , et al. March 8, 2 | 2005-03-08 |
Methods of forming a semiconductor device having a metal gate electrode and associated devices
App 20050020042 - Heo, Seong-Jun ; et al. | 2005-01-27 |
Nickel alloy salicide transistor structure and method for manufacturing same
App 20040266182 - Ku, Ja-Hum ; et al. | 2004-12-30 |
Methods of fabricating a semiconductor device having MOS transistor with strained channel
App 20040253791 - Sun, Min-Chul ; et al. | 2004-12-16 |
Semiconductor structure having low resistance and method of manufacturing same
App 20040238876 - Youn, Sunpil ; et al. | 2004-12-02 |
Nickel salicide process with reduced dopant deactivation
App 20040209432 - Ku, Ja-Hum ; et al. | 2004-10-21 |
Method of fabricating semiconductor device having metal conducting layer
Grant 6,797,559 - Lee , et al. September 28, 2 | 2004-09-28 |
Method of forming a metal gate electrode
Grant 6,764,961 - Ku , et al. July 20, 2 | 2004-07-20 |
Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film
App 20040132268 - Koo, Kyeong-mo ; et al. | 2004-07-08 |
Methods of fabricating a semiconductor device having a metal gate pattern
App 20040132272 - Ku, Ja-Hum ; et al. | 2004-07-08 |
Method for fabricating semiconductor device using a nickel salicide process
App 20040097060 - San, Min-Chul ; et al. | 2004-05-20 |
Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer
App 20040014330 - Ku, Ja-Hum ; et al. | 2004-01-22 |
Methods of fabricating integrated circuit gates by pretreating prior to oxidizing
App 20030224590 - Cho, Jun-Kyu ; et al. | 2003-12-04 |
Method of fabricating semiconductor device having metal conducting layer
App 20030190800 - Lee, Chang-Won ; et al. | 2003-10-09 |
Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
Grant 6,624,496 - Ku , et al. September 23, 2 | 2003-09-23 |
Method of forming a metal gate electrode
App 20020137321 - Ku, Ja-Hum ; et al. | 2002-09-26 |
Method of forming a metal gate
App 20020127888 - Cho, Mahn-Ho ; et al. | 2002-09-12 |
Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
App 20020090795 - Ahn, Dong-Ho ; et al. | 2002-07-11 |
Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
Grant 6,383,877 - Ahn , et al. May 7, 2 | 2002-05-07 |
Method of forming self-aligned silicide in semiconductor device
Grant 6,329,276 - Ku , et al. December 11, 2 | 2001-12-11 |
Transistor having reverse self-aligned structure
Grant 6,218,690 - Kim , et al. April 17, 2 | 2001-04-17 |
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