Krishnan; Anand T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Krishnan; Anand T..The latest application filed is for "integrated circuit die and method of making".

Company Profile

0.10.14

Krishnan; Anand T. - Irving TX
Krishnan; Anand T. - Farmers Branch TX
Krishnan; Anand T. - Richardson TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated Circuit Die And Method Of Making App 20140024144 - Jain; Palkesh ; et al.	2014-01-23
Integrated Circuit Die And Method Of Making App 20130161718 - Jain; Palkesh ; et al.	2013-06-27
Current-voltage-based method for evaluating thin dielectrics based on interface traps Grant 7,737,717 - Nicollian , et al. June 15, 2	2010-06-15
Method and system for reducing charge damage in silicon-on-insulator technology Grant 7,638,412 - Gallia , et al. December 29, 2	2009-12-29
Current-voltage-based Method For Evaluating Thin Dielectrics Based On Interface Traps App 20090224795 - Nicollian; Paul Edward ; et al.	2009-09-10
Method to identify or screen VMIN drift on memory cells during burn-in or operation Grant 7,450,452 - Rosal , et al. November 11, 2	2008-11-11
Method to Identify or Screen VMIN Drift on Memory Cells During Burn-In or Operation App 20070297254 - Rosal; Juan A. ; et al.	2007-12-27
Method and system for reducing charge damage in silicon-on-insulator technology App 20070264804 - Gallia; James D. ; et al.	2007-11-15
Semiconductor device fabricated using a carbon-containing film as a contact etch stop layer App 20070210421 - Bu; Haowen ; et al.	2007-09-13
Method and system for reducing charge damage in silicon-on-insulator technology Grant 7,262,468 - Gallia , et al. August 28, 2	2007-08-28
System and method for accurate negative bias temperature instability characterization Grant 7,218,132 - Krishnan , et al. May 15, 2	2007-05-15
System and method for accurate negative bias temperature instability characterization Grant 7,212,023 - Krishnan , et al. May 1, 2	2007-05-01
Interface improvement by stress application during oxide growth through use of backside films Grant 7,208,380 - Krishnan , et al. April 24, 2	2007-04-24
Method of manufacturing antenna proximity lines Grant 7,071,092 - Krishnan , et al. July 4, 2	2006-07-04
System and method for accurate negative bias temperature instability characterization App 20060076971 - Krishnan; Anand T. ; et al.	2006-04-13
System and method for accurate negative bias temperature instability characterization App 20060049842 - Krishnan; Anand T. ; et al.	2006-03-09
Integrated circuit having antenna proximity lines coupled to the semiconductor substrate contacts Grant 6,969,902 - Krishnan , et al. November 29, 2	2005-11-29
Interface improvement by stress application during oxide growth through use of backside films App 20050208776 - Krishnan, Anand T. ; et al.	2005-09-22
Semiconductor antenna proximity lines App 20050133826 - Krishnan, Anand T. ; et al.	2005-06-23
Semiconductor antenna proximity lines App 20040183102 - Krishnan, Anand T. ; et al.	2004-09-23
Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process Grant 6,709,932 - Krishnan , et al. March 23, 2	2004-03-23
Method For Improving Gate Oxide Integrity & Interface Quality In A Multi-gate Oxidation Process App 20040043567 - Krishnan, Anand T. ; et al.	2004-03-04
Method and system for reducing charge damage in silicon-on-insulator technology App 20030122190 - Gallia, James D. ; et al.	2003-07-03

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