Krauch; Ulrich

Patent Applications and Registrations

Patent applications and USPTO patent grants for Krauch; Ulrich.The latest application filed is for "circuit for addition of multiple binary numbers".

Company Profile

5.14.15

Krauch; Ulrich - Dettenhausen DE
Krauch; Ulrich - Boeblingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit for addition of multiple binary numbers Grant 10,528,323 - Beck , et al. J	2020-01-07
Integrated circuit chip and a method for testing the same Grant 10,317,465 - Haller , et al.	2019-06-11
Circuit For Addition Of Multiple Binary Numbers App 20190034165 - BECK; Manuel ; et al.	2019-01-31
Circuit for addition of multiple binary numbers Grant 10,168,991 - Beck , et al. J	2019-01-01
Integrated Circuit Chip And A Method For Testing The Same App 20180231607 - Haller; Wilhelm ; et al.	2018-08-16
Integrated circuit chip and a method for testing the same Grant 10,006,965 - Haller , et al. June 26, 2	2018-06-26
Detecting dispensable inverter chains in a circuit design Grant 9,996,656 - Krauch , et al. June 12, 2	2018-06-12
Circuit For Addition Of Multiple Binary Numbers App 20180088907 - BECK; Manuel ; et al.	2018-03-29
Detecting Dispensable Inverter Chains In A Circuit Design App 20170371998 - KRAUCH; Ulrich ; et al.	2017-12-28
Current-mode sense amplifier Grant 9,595,304 - Fritsch , et al. March 14, 2	2017-03-14
Integrated Circuit Chip And A Method For Testing The Same App 20170003345 - Haller; Wilhelm ; et al.	2017-01-05
Integrated circuit chip and a method for testing the same Grant 9,506,986 - Haller , et al. November 29, 2	2016-11-29
Method and system to fix early mode slacks in a circuit design Grant 9,058,456 - Haller , et al. June 16, 2	2015-06-16
Integrated Circuit Chip and a Method for Testing the Same App 20150160293 - Haller; Wilhelm ; et al.	2015-06-11
Method And System To Fix Early Mode Slacks In A Circuit Design App 20140089880 - Haller; Wilhelm ; et al.	2014-03-27
Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic Grant 8,612,500 - Haller , et al. December 17, 2	2013-12-17
Simd Accelerator For Data Comparison App 20130227250 - Haller; Wilhelm ; et al.	2013-08-29
Generation of an end point report for a timing simulation of an integrated circuit Grant 8,522,182 - Krauch , et al. August 27, 2	2013-08-27
Generation Of An End Point Report For A Timing Simulation Of An Integrated Circuit App 20120246606 - KRAUCH; Ulrich ; et al.	2012-09-27
Method To Perform A Subtraction Of Two Operands In A Binary Arithmetic Unit Plus Arithmetic Unit To Perform Such A Method App 20090112963 - Haller; Wilhelm ; et al.	2009-04-30
Layout Generator for Routing and Designing an LSI App 20080301616 - Krauch; Ulrich ; et al.	2008-12-04
Method And Decimal Arithmetic Logic Unit Structure To Generate A Magnitude Result of a Mathematic App 20080177816 - Haller; Wilhelm ; et al.	2008-07-24
Automatic method for routing and designing an LSI Grant 7,401,312 - Krauch , et al. July 15, 2	2008-07-15
Method To Perform A Subtraction Of Two Operands In A Binary Arithmetic Unit Plus Arithmetic Unit To Perform Such A Method App 20080071852 - Haller; Wilhelm ; et al.	2008-03-20
Automatic method for routing and designing an LSI App 20050132319 - Krauch, Ulrich ; et al.	2005-06-16
Storage cell with integrated soft error detection and correction Grant 6,668,341 - Krauch , et al. December 23, 2	2003-12-23

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