Kovacs-Birkas; Attila
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kovacs-Birkas; Attila.The latest application filed is for "calibrating a wire load model for an integrated circuit".
- Kovacs-Birkas; Attila - Santa Clara CA
| Patent | Date |
|---|---|
| Calibrating a wire load model for an integrated circuit Grant 7,149,991 - Kovacs-Birkas , et al. December 12, 2 | 2006-12-12 |
| Cell modeling in the design of an integrated circuit Grant 6,985,843 - Kovacs-Birkas January 10, 2 | 2006-01-10 |
| Calibrating a wire load model for an integrated circuit App 20040205683 - Kovacs-Birkas, Attila ; et al. | 2004-10-14 |
| Cell modeling in the design of an integrated circuit App 20020199155 - Kovacs-Birkas, Attila | 2002-12-26 |
| Timing optimization and timing closure for integrated circuit models Grant 6,487,705 - Roethig , et al. November 26, 2 | 2002-11-26 |
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