| Patent | Date |
|---|
Operand pool instruction reservation clustering in a scheduler circuit in a processor
Grant 11,392,410 - Priyadarshi , et al. July 19, 2 | 2022-07-19 |
Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor
Grant 11,392,387 - Kothinti Naresh , et al. July 19, 2 | 2022-07-19 |
Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor
Grant 11,327,763 - Perais , et al. May 10, 2 | 2022-05-10 |
Predicting Load-based Control Independent (ci) Register Data Independent (di) (cirdi) Instructions As Ci Memory Data Dependent (dd) (cimdd) Instructions For Replay In Speculative Misprediction Recovery In A Processor
App 20220137977 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2022-05-05 |
Restoring Speculative History Used For Making Speculative Predictions For Instructions Processed In A Processor Employing Control Independence Techniques
App 20220113976 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2022-04-14 |
Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor
Grant 11,269,642 - Kothinti Naresh March 8, 2 | 2022-03-08 |
Opportunistic Consumer Instruction Steering Based On Producer Instruction Value Prediction In A Multi-cluster Processor
App 20210389951 - PERAIS; Arthur ; et al. | 2021-12-16 |
Operand Pool Instruction Reservation Clustering In A Scheduler Circuit In A Processor
App 20210318905 - PRIYADARSHI; Shivam ; et al. | 2021-10-14 |
Tracking and communication of direct/indirect source dependencies of producer instructions executed in a processor to source dependent consumer instructions to facilitate processor optimizations
Grant 11,068,272 - Kothinti Naresh July 20, 2 | 2021-07-20 |
Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative
Grant 11,061,824 - Kothinti Naresh , et al. July 13, 2 | 2021-07-13 |
Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor
Grant 11,061,683 - Kothinti Naresh , et al. July 13, 2 | 2021-07-13 |
Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor
Grant 11,061,677 - Seth , et al. July 13, 2 | 2021-07-13 |
Systems and methods for processing instructions having wide immediate operands
Grant 11,036,512 - Perais , et al. June 15, 2 | 2021-06-15 |
Dynamic Hammock Branch Training For Branch Hammock Detection In An Instruction Stream Executing In A Processor
App 20210089313 - KOTHINTI NARESH; Vignyan Reddy | 2021-03-25 |
Systems And Methods For Processing Instructions Having Wide Immediate Operands
App 20210089308 - PERAIS; Arthur ; et al. | 2021-03-25 |
Tracking And Communication Of Direct/indirect Source Dependencies Of Producer Instructions Executed In A Processor To Source Dependent Consumer Instructions To Facilitate Processor Optimizations
App 20210089312 - KOTHINTI NARESH; Vignyan Reddy | 2021-03-25 |
Deferring Cache State Updates In A Non-speculative Cache Memory In A Processor-based System In Response To A Speculative Data Request Until The Speculative Data Request Becomes Non-speculative
App 20210064541 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2021-03-04 |
Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices
Grant 10,929,139 - Hsu , et al. February 23, 2 | 2021-02-23 |
Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices
Grant 10,896,041 - Priyadarshi , et al. January 19, 2 | 2021-01-19 |
Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor
Grant 10,877,768 - Priyadarshi , et al. December 29, 2 | 2020-12-29 |
Limiting Replay Of Load-based Control Independent (ci) Instructions In Speculative Misprediction Recovery In A Processor
App 20200394040 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2020-12-17 |
Reduction Of Data Cache Access In A Processing System
App 20200310814 - KOTHINTI NARESH; Vignyan Reddy | 2020-10-01 |
Deadlock free resource management in block based computing architectures
Grant 10,783,011 - Kothinti Naresh , et al. Sept | 2020-09-22 |
Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
Grant 10,725,782 - Krishna , et al. | 2020-07-28 |
Providing Predictive Instruction Dispatch Throttling To Prevent Resource Overflows In Out-of-order Processor (oop)-based Devices
App 20200104163 - Hsu; Lisa Ru-feng ; et al. | 2020-04-02 |
Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system
Grant 10,437,592 - Krishna , et al. O | 2019-10-08 |
Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt
Grant 10,255,074 - Kothinti Naresh , et al. | 2019-04-09 |
Deadlock Free Resource Management In Block Based Computing Architectures
App 20190087241 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2019-03-21 |
Select In-order Instruction Pick Using An Out Of Order Instruction Picker
App 20190087184 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2019-03-21 |
Providing Variable Interpretation Of Usefulness Indicators For Memory Tables In Processor-based Systems
App 20190079772 - Krishna; Anil ; et al. | 2019-03-14 |
Reduced Logic Level Operation Folding Of Context History In A History Register In A Prediction System For A Processor-based System
App 20190065196 - Krishna; Anil ; et al. | 2019-02-28 |
PROVIDING EFFICIENT RECURSION HANDLING USING COMPRESSED RETURN ADDRESS STACKS (CRASs) IN PROCESSOR-BASED SYSTEMS
App 20190065197 - Kothinti Naresh; Vignyan Reddy ; et al. | 2019-02-28 |
Caching Instruction Block Header Data In Block Architecture Processor-based Systems
App 20190065060 - Krishna; Anil ; et al. | 2019-02-28 |
Reusing Trained Prefetchers
App 20180089085 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2018-03-29 |
Performing Distributed Branch Prediction Using Fused Processor Cores In Processor-based Systems
App 20180081690 - Krishna; Anil ; et al. | 2018-03-22 |
Memory Violation Prediction
App 20180081806 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2018-03-22 |
Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor
Grant 9,830,152 - Kothinti Naresh , et al. November 28, 2 | 2017-11-28 |
Providing References To Previously Decoded Instructions Of Recently-provided Instructions To Be Executed By A Processor
App 20170277536 - Kothinti Naresh; Vignyan Reddy ; et al. | 2017-09-28 |
Selective Storing Of Previously Decoded Instructions Of Frequently-called Instruction Sequences In An Instruction Sequence Buffer To Be Executed By A Processor
App 20170177366 - Kothinti Naresh; Vignyan Reddy ; et al. | 2017-06-22 |
Selective Flushing Of Instructions In An Instruction Pipeline In A Processor Back To An Execution-resolved Target Address, In Response To A Precise Interrupt
App 20170075692 - Kothinti Naresh; Vignyan Reddy ; et al. | 2017-03-16 |
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