Kotecha, Harish N.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kotecha, Harish N..The latest application filed is for "instant yogurt food product".
- Kotecha, Harish N. - Cedar Park TX
- Kotecha; Harish N. - Manassas VA
- Kotecha; Harish N. - Essex Junction VT
| Patent | Date |
|---|---|
| Instant yogurt food product App 20050112239 - Rudin, Richard E. ; et al. | 2005-05-26 |
| Method for fabricating high circuit density, self-aligned metal linens to contact windows Grant 5,143,820 - Kotecha , et al. September 1, 1 | 1992-09-01 |
| Multiple ROM data state, read/write memory cell Grant 4,805,142 - Bertin , et al. February 14, 1 | 1989-02-14 |
| Quaternary FET read only memory Grant RE32,401 - Beilstein, Jr. , et al. April 14, 1 | 1987-04-14 |
| Resistor personalized memory device using a resistive gate fet Grant 4,583,201 - Bertin , et al. April 15, 1 | 1986-04-15 |
| Method of making ROM/PLA semiconductor device by late stage personalization Grant 4,536,944 - Bracco , et al. August 27, 1 | 1985-08-27 |
| Integrated dynamic RAM and ROS Grant 4,488,265 - Kotecha December 11, 1 | 1984-12-11 |
| Two carrier dual injector apparatus Grant 4,472,726 - DiMaria , et al. September 18, 1 | 1984-09-18 |
| Non-volatile static RAM cell with enhanced conduction insulators Grant 4,399,522 - Kotecha August 16, 1 | 1983-08-16 |
| Non-volatile RAM cell with enhanced conduction insulators Grant 4,388,704 - Bertin , et al. June 14, 1 | 1983-06-14 |
| Electrically alterable double dense memory Grant 4,380,057 - Kotecha , et al. April 12, 1 | 1983-04-12 |
| Non-volatile dynamic RAM cell Grant 4,363,110 - Kalter , et al. December 7, 1 | 1982-12-07 |
| Process for making a dual implanted drain extension for bucket brigade device tetrode structure Grant 4,358,890 - Heller , et al. November 16, 1 | 1982-11-16 |
| Three terminal electrically erasable programmable read only memory Grant 4,336,603 - Kotecha , et al. June 22, 1 | 1982-06-22 |
| Low voltage electrically erasable programmable read only memory Grant 4,334,292 - Kotecha June 8, 1 | 1982-06-08 |
| Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices Grant 4,329,186 - Kotecha , et al. May 11, 1 | 1982-05-11 |
| Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations Grant 4,276,095 - Beilstein, Jr. , et al. June 30, 1 | 1981-06-30 |
| Quaternary FET read only memory Grant 4,202,044 - Beilstein, Jr. , et al. May 6, 1 | 1980-05-06 |
| Inverter with improved load line characteristic Grant 4,138,782 - De la Moneda , et al. February 13, 1 | 1979-02-13 |
| Two and three mask process for IGFET fabrication Grant 4,102,733 - De La Moneda , et al. July 25, 1 | 1978-07-25 |
| FET inverter with isolated substrate load Grant 4,072,868 - De La Moneda , et al. February 7, 1 | 1978-02-07 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 