Korsh; George J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Korsh; George J..The latest application filed is for "guard ring extension to prevent reliability failures".

Company Profile

0.19.10

Korsh; George J. - Redwod City CA
Korsh; George J. - Redwood City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Guard ring extension to prevent reliability failures Grant 7,972,909 - Chang , et al. July 5, 2	2011-07-05
Guard ring extension to prevent reliability failures Grant 7,968,976 - Chang , et al. June 28, 2	2011-06-28
Guard Ring Extension To Prevent Reliability Failures App 20100187528 - Chang; Nicole Meier ; et al.	2010-07-29
Guard Ring Extension To Prevent Realiability Failures App 20090200548 - Chang; Nicole Meier ; et al.	2009-08-13
Guard ring extension to prevent reliability failures Grant 7,566,915 - Chang , et al. July 28, 2	2009-07-28
Guard ring extension to prevent reliability failures App 20080157284 - Chang; Nicole Meier ; et al.	2008-07-03
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system Grant 7,035,151 - Tran , et al. April 25, 2	2006-04-25
Column redundancy for digital multilevel nonvolatile memory Grant 6,992,937 - Tran , et al. January 31, 2	2006-01-31
Column redundancy for digital multilevel nonvolatile memory App 20050024956 - Tran, Hieu Van ; et al.	2005-02-03
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system App 20040233716 - Tran, Hieu van ; et al.	2004-11-25
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system Grant 6,751,118 - Tran , et al. June 15, 2	2004-06-15
Non-volatile flash fuse element Grant 6,590,825 - Tran , et al. July 8, 2	2003-07-08
Non-volatile flash fuse element App 20030086326 - Tran, Hieu Van ; et al.	2003-05-08
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system Grant 6,519,180 - Tran , et al. February 11, 2	2003-02-11
Precision programming of nonvolatile memory cells Grant 6,487,116 - Khan , et al. November 26, 2	2002-11-26
Testing of multilevel semiconductor memory Grant 6,396,742 - Korsh , et al. May 28, 2	2002-05-28
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system App 20020041516 - Tran, Hieu Van ; et al.	2002-04-11
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system App 20020039322 - Tran, Hieu Van ; et al.	2002-04-04
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system App 20020036920 - Tran, Hieu Van ; et al.	2002-03-28
Precision programming of nonvolatile memory cells App 20010050863 - Khan, Sakhawat M. ; et al.	2001-12-13
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system Grant 6,282,145 - Tran , et al. August 28, 2	2001-08-28
Precision programming of nonvolatile memory cells Grant 6,038,174 - Khan , et al. March 14, 2	2000-03-14
Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell Grant 5,901,089 - Korsh , et al. May 4, 1	1999-05-04
Precision programming of nonvolatile memory cells Grant 5,870,335 - Khan , et al. February 9, 1	1999-02-09
Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell Grant 5,815,439 - Korsh , et al. September 29, 1	1998-09-29
High speed, low voltage non-volatile memory Grant 5,587,951 - Jazayeri , et al. December 24, 1	1996-12-24
Transistor construction for low noise output driver Grant 4,949,139 - Korsh , et al. August 14, 1	1990-08-14
Method of making EPROM cell with reduced programming voltage Grant 4,519,849 - Korsh , et al. May 28, 1	1985-05-28
EPROM Cell with reduced programming voltage and method of fabrication Grant 4,412,310 - Korsh , et al. October 25, 1	1983-10-25

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.