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name:-0.023476123809814
name:-0.026655912399292
name:-0.00038695335388184
Kopcsay; Gerard V. Patent Filings

Kopcsay; Gerard V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kopcsay; Gerard V..The latest application filed is for "multi-petascale highly efficient parallel supercomputer".

Company Profile
0.26.16
  • Kopcsay; Gerard V. - Yorktown Heights NY
  • Kopcsay; Gerard V. - Yorktown Heigths NY
  • Kopcsay, Gerard V - Yorktown Heights NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Multi-petascale highly efficient parallel supercomputer
Grant 9,971,713 - Asaad , et al. May 15, 2
2018-05-15
Multi-petascale Highly Efficient Parallel Supercomputer
App 20160011996 - Asaad; Sameh ;   et al.
2016-01-14
Multi-petascale highly efficient parallel supercomputer
Grant 9,081,501 - Asaad , et al. July 14, 2
2015-07-14
System-wide power management control via clock distribution network
Grant 9,037,892 - Coteus , et al. May 19, 2
2015-05-19
Non-volatile memory for checkpoint storage
Grant 8,788,879 - Blumrich , et al. July 22, 2
2014-07-22
Massively parallel supercomputer
Grant 8,667,049 - Blumrich , et al. March 4, 2
2014-03-04
Reproducibility in a multiprocessor system
Grant 8,595,554 - Bellofatto , et al. November 26, 2
2013-11-26
Global synchronization of parallel processors using clock pulse width modulation
Grant 8,412,974 - Chen , et al. April 2, 2
2013-04-02
Novel Massively Parallel Supercomputer
App 20120311299 - Blumrich; Matthias A. ;   et al.
2012-12-06
System-wide Power Management Control Via Clock Distribution Network
App 20120266008 - Coteus; Paul W. ;   et al.
2012-10-18
Massively parallel supercomputer
Grant 8,250,133 - Blumrich , et al. August 21, 2
2012-08-21
System and method implementing short-pulse propagation technique on production-level boards with incremental accuracy and productivity levels
Grant 8,035,409 - Deutsch , et al. October 11, 2
2011-10-11
Multi-petascale Highly Efficient Parallel Supercomputer
App 20110219208 - Asaad; Sameh ;   et al.
2011-09-08
Non-volatile Memory For Checkpoint Storage
App 20110173488 - Blumrich; Matthias A. ;   et al.
2011-07-14
Reproducibility In A Multiprocessor System
App 20110119521 - Bellofatto; Ralph A. ;   et al.
2011-05-19
Global Synchronization Of Parallel Processors Using Clock Pulse Width Modulation
App 20110119475 - Chen; Dong ;   et al.
2011-05-19
Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
Grant 7,844,435 - Bowen , et al. November 30, 2
2010-11-30
System And Method Implementing Short-pulse Propagation Technique On Production-level Boards With Incremental Accuracy And Productivity Levels
App 20100277197 - Deutsch; Alina ;   et al.
2010-11-04
Data capture technique for high speed signaling
Grant 7,817,585 - Barrett , et al. October 19, 2
2010-10-19
Ultrascalable petaflop parallel supercomputer
Grant 7,761,687 - Blumrich , et al. July 20, 2
2010-07-20
Novel Massively Parallel Supercomputer
App 20090259713 - Blumrich; Matthias A. ;   et al.
2009-10-15
Massively parallel supercomputer
Grant 7,555,566 - Blumrich , et al. June 30, 2
2009-06-30
Ultrascalable Petaflop Parallel Supercomputer
App 20090006808 - Blumrich; Matthias A. ;   et al.
2009-01-01
Global interrupt and barrier networks
Grant 7,444,385 - Blumrich , et al. October 28, 2
2008-10-28
Integrated Circuit Chip Having On-Chip Signal Integrity and Noise Verification Using Frequency Dependent RLC Extraction and Modeling Techniques
App 20080072189 - Bowen; Michael A. ;   et al.
2008-03-20
Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
Grant 7,319,946 - Bowen , et al. January 15, 2
2008-01-15
Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
Grant 7,093,206 - Anand , et al. August 15, 2
2006-08-15
Method to include delta-I noise on chip using lossy transmission line representation for the power mesh
Grant 6,963,204 - Deutsch , et al. November 8, 2
2005-11-08
Method To Include Delta-i Noise On Chip Using Lossy Transmission Line Representation For The Power Mesh
App 20050218908 - Deutsch, Alina ;   et al.
2005-10-06
Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
App 20050086615 - Anand, Minakshisundaran B. ;   et al.
2005-04-21
Novel massively parallel supercomputer
App 20040103218 - Blumrich, Matthias A ;   et al.
2004-05-27
Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
App 20040078176 - Bowen, Michael A. ;   et al.
2004-04-22
Global interrupt and barrier networks
App 20040068599 - Blumrich, Matthias A. ;   et al.
2004-04-08
Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation
Grant 6,418,401 - Dansky , et al. July 9, 2
2002-07-09
Methods for the measurement of the frequency dependent complex propagation matrix, impedance matrix and admittance matrix of coupled transmission lines
Grant 5,502,392 - Arjavalingam , et al. March 26, 1
1996-03-26
LSI Chip carrier with buried repairable capacitor with low inductance leads
Grant 4,453,176 - Chance , et al. June 5, 1
1984-06-05

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