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Feedback programmable data strobe enable architecture for DDR memory applications Grant 8,819,354 - Seto , et al. August 26, 2 | 2014-08-26 |
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High Speed Multiple Memory Interface I/o Cell App 20110084725 - Bhakta; Dharmesh ;   et al. | 2011-04-14 |
High speed multiple memory interface I/O cell Grant 7,876,123 - Bhakta , et al. January 25, 2 | 2011-01-25 |
Configurable high-speed memory interface subsystem Grant 7,865,661 - Butt , et al. January 4, 2 | 2011-01-04 |
Apparatus and systems for VT invariant DDR3 SDRAM write leveling Grant 7,839,716 - Kong , et al. November 23, 2 | 2010-11-23 |
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Multiple memory standard physical layer macro function App 20090091987 - Butt; Derrick Sai-Tang ;   et al. | 2009-04-09 |
High speed multiple memory interface I/O cell App 20090091349 - Bhakta; Dharmesh ;   et al. | 2009-04-09 |
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System and method for compensating for PVT variation effects on the delay line of a clock signal App 20080150610 - Magee; Terence ;   et al. | 2008-06-26 |
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