loadpatents
name:-0.022001028060913
name:-0.027976989746094
name:-0.00050187110900879
Kong; Cheng-Gang Patent Filings

Kong; Cheng-Gang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kong; Cheng-Gang.The latest application filed is for "high speed multiple memory interface i/o cell".

Company Profile
0.26.18
  • Kong; Cheng-Gang - Saratoga CA
  • Kong; Cheng-Gang - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
High speed multiple memory interface I/O cell
Grant 8,912,818 - Bhakta , et al. December 16, 2
2014-12-16
Feedback programmable data strobe enable architecture for DDR memory applications
Grant 8,819,354 - Seto , et al. August 26, 2
2014-08-26
Generic low power strobe based system and method for interfacing memory controller and source synchronous memory
Grant 8,743,634 - Magee , et al. June 3, 2
2014-06-03
Method and computer program for generating grounded shielding wires for signal wiring
Grant 8,516,425 - Nikitin , et al. August 20, 2
2013-08-20
Non-linear common coarse delay system and method for delaying data strobe
Grant 8,453,096 - Magee , et al. May 28, 2
2013-05-28
High Speed Multiple Memory Interface I/o Cell
App 20130049799 - Bhakta; Dharmesh ;   et al.
2013-02-28
High speed multiple memory interface I/O cell
Grant 8,324,927 - Bhakta , et al. December 4, 2
2012-12-04
Signal Delay Skew Reduction System
App 20120278783 - Nikitin; Andrey ;   et al.
2012-11-01
Method and apparatus for balancing signal delay skew
Grant 8,239,813 - Nikitin , et al. August 7, 2
2012-08-07
Generic Low Power Strobe Based System And Method For Interfacing Memory Controller And Source Synchronous Memory
App 20120195141 - Magee; Terence J. ;   et al.
2012-08-02
Non-linear Common Coarse Delay System And Method For Delaying Data Strobe
App 20120194248 - Magee; Terence J. ;   et al.
2012-08-02
Memory interface architecture for maximizing access timing margin
Grant 8,230,143 - Seto , et al. July 24, 2
2012-07-24
Signal Delay Skew Reduction System
App 20110258587 - Nikitin; Andrey ;   et al.
2011-10-20
Signal delay skew reduction system
Grant 7,996,804 - Nikitin , et al. August 9, 2
2011-08-09
Multiple memory standard physical layer macro function
Grant 7,969,799 - Butt , et al. June 28, 2
2011-06-28
High Speed Multiple Memory Interface I/o Cell
App 20110084725 - Bhakta; Dharmesh ;   et al.
2011-04-14
High speed multiple memory interface I/O cell
Grant 7,876,123 - Bhakta , et al. January 25, 2
2011-01-25
Configurable high-speed memory interface subsystem
Grant 7,865,661 - Butt , et al. January 4, 2
2011-01-04
Apparatus and systems for VT invariant DDR3 SDRAM write leveling
Grant 7,839,716 - Kong , et al. November 23, 2
2010-11-23
Apparatus And Systems For Vt Invariant Ddr3 Sdram Write Leveling
App 20100157700 - Kong; Cheng-Gang ;   et al.
2010-06-24
System and method for providing swap path voltage and temperature compensation
Grant 7,571,396 - Hughes , et al. August 4, 2
2009-08-04
Signal Delay Skew Reduction System
App 20090187873 - Nikitin; Andrey ;   et al.
2009-07-23
Multiple memory standard physical layer macro function
App 20090091987 - Butt; Derrick Sai-Tang ;   et al.
2009-04-09
High speed multiple memory interface I/O cell
App 20090091349 - Bhakta; Dharmesh ;   et al.
2009-04-09
Configurable high-speed memory interface subsystem
App 20090043955 - Butt; Derrick Sai-Tang ;   et al.
2009-02-12
System and method for compensating for PVT variation effects on the delay line of a clock signal
Grant 7,454,303 - Magee , et al. November 18, 2
2008-11-18
Configurable high-speed memory interface subsystem
Grant 7,437,500 - Butt , et al. October 14, 2
2008-10-14
System and method for compensating for PVT variation effects on the delay line of a clock signal
App 20080150610 - Magee; Terence ;   et al.
2008-06-26
System and method for providing swap path voltage and temperature compensation
App 20080068911 - Hughes; Thomas ;   et al.
2008-03-20
Apparatus and methods for improved input/output cells
Grant 7,239,170 - Suen , et al. July 3, 2
2007-07-03
Configurable high-speed memory interface subsystem
App 20070033337 - Butt; Derrick Sai-Tang ;   et al.
2007-02-08
Feedback programmable data strobe enable architecture for DDR memory applications
App 20060288175 - Seto; Hui-Yin ;   et al.
2006-12-21
Wide-range programmable delay line
Grant 7,119,596 - Kong , et al. October 10, 2
2006-10-10
Memory interface architecture for maximizing access timing margin
App 20060224847 - Seto; Hui-Yin ;   et al.
2006-10-05
Wide-range programmable delay line
App 20060132210 - Kong; Cheng-Gang ;   et al.
2006-06-22
Apparatus and methods for improved input/output cells
App 20050010833 - Suen, Victor ;   et al.
2005-01-13
Streamlined instruction processor
Grant 4,926,323 - Baror , et al. May 15, 1
1990-05-15
General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance
Grant 4,777,588 - Case , et al. October 11, 1
1988-10-11
System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
Grant 4,777,587 - Case , et al. October 11, 1
1988-10-11
Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
Grant 4,734,852 - Johnson , et al. March 29, 1
1988-03-29

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