Kondapalli; Venu M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kondapalli; Venu M..The latest application filed is for "fpga with a plurality of input reference voltage levels".

Company Profile

0.30.1

Kondapalli; Venu M. - Sunnyvale CA
Kondapalli; Venu M. - Suunyvale CA
Kondapalli; Venu M. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode Grant 7,804,719 - Chirania , et al. September 28, 2	2010-09-28
Apparatus and method for reconfiguring a programmable logic device Grant 7,518,396 - Kondapalli , et al. April 14, 2	2009-04-14
Method and apparatus for a programmable level translator Grant 7,456,654 - Rau , et al. November 25, 2	2008-11-25
Interconnect driver circuits for dynamic logic Grant 7,382,157 - Young , et al. June 3, 2	2008-06-03
Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure Grant 7,375,552 - Young , et al. May 20, 2	2008-05-20
Data monitoring for single event upset in a programmable logic device Grant 7,283,409 - Voogel , et al. October 16, 2	2007-10-16
Methods and structures of providing modular integrated circuits Grant 7,284,226 - Kondapalli October 16, 2	2007-10-16
Programmable logic block with carry chains providing lookahead functions of different lengths Grant 7,268,587 - Pham , et al. September 11, 2	2007-09-11
Programmable lookup table with dual input and output terminals in RAM mode Grant 7,265,576 - Kondapalli , et al. September 4, 2	2007-09-04
Programmable lookup table with dual input and output terminals in shift register mode Grant 7,215,138 - Kondapalli , et al. May 8, 2	2007-05-08
Programmable logic block having improved performance when functioning in shift register mode Grant 7,202,697 - Kondapalli , et al. April 10, 2	2007-04-10
Method of measuring performance of a semiconductor device and circuit for the same Grant 7,119,570 - Chirania , et al. October 10, 2	2006-10-10
High performance programmable logic devices utilizing dynamic circuitry Grant 7,116,131 - Chirania , et al. October 3, 2	2006-10-03
Data monitoring for single event upset in a programmable logic device Grant 7,109,746 - Voogel , et al. September 19, 2	2006-09-19
Method and apparatus for voltage regulation within an integrated circuit Grant 7,109,783 - Kondapalli , et al. September 19, 2	2006-09-19
Programmable circuit optionally configurable as a lookup table or a wide multiplexer Grant 7,075,333 - Chaudhary , et al. July 11, 2	2006-07-11
Six-input look-up table and associated memory control circuitry for use in a field programmable gate array Grant 7,075,332 - Young , et al. July 11, 2	2006-07-11
Six-input look-up table for use in a field programmable gate array Grant 7,061,271 - Young , et al. June 13, 2	2006-06-13
PLD lookup table including transistors of more than one oxide thickness Grant 7,053,654 - Young , et al. May 30, 2	2006-05-30
Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs Grant 6,998,872 - Chirania , et al. February 14, 2	2006-02-14
Integrated circuit multiplexer including transistors of more than one oxide thickness Grant 6,949,951 - Young , et al. September 27, 2	2005-09-27
PLD lookup table including transistors of more than one oxide thickness Grant 6,768,338 - Young , et al. July 27, 2	2004-07-27
Integrated circuit multiplexer including transistors of more than one oxide thickness Grant 6,768,335 - Young , et al. July 27, 2	2004-07-27
Method and apparatus for voltage regulation within an integrated circuit Grant 6,753,722 - Kondapalli , et al. June 22, 2	2004-06-22
Programmable logic device with partial battery backup Grant 6,441,641 - Pang , et al. August 27, 2	2002-08-27
Nonvolatile/battery-backed key in PLD Grant 6,366,117 - Pang , et al. April 2, 2	2002-04-02
FPGA with a plurality of input reference voltage levels App 20020005735 - Goetting, F. Erich ; et al.	2002-01-17
FPGA with a plurality of input reference voltage levels Grant 6,294,930 - Goetting , et al. September 25, 2	2001-09-25
FPGA with a plurality of I/O voltage levels Grant 6,049,227 - Goetting , et al. April 11, 2	2000-04-11
Input/output buffer supporting multiple I/O standards Grant 5,958,026 - Goetting , et al. September 28, 1	1999-09-28
FPGA with a plurality of I/O voltage levels Grant 5,877,632 - Goetting , et al. March 2, 1	1999-03-02

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