loadpatents
name:-0.020684957504272
name:-0.01623010635376
name:-0.00052690505981445
Kolan; Ravi Kanth Patent Filings

Kolan; Ravi Kanth

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kolan; Ravi Kanth.The latest application filed is for "packaging structural member".

Company Profile
0.18.17
  • Kolan; Ravi Kanth - Singapore SG
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Packaging structural member
Grant 9,704,726 - Toh , et al. July 11, 2
2017-07-11
Packaging Structural Member
App 20160005629 - TOH; Chin Hock ;   et al.
2016-01-07
Packaging structural member
Grant 9,142,487 - Toh , et al. September 22, 2
2015-09-22
Interposer for semiconductor package
Grant 8,772,921 - Toh , et al. July 8, 2
2014-07-08
Through silicon via dies and packages
Grant 8,741,762 - Liu , et al. June 3, 2
2014-06-03
Through Silicon Via Dies And Packages
App 20140045301 - LIU; Hao ;   et al.
2014-02-13
Through silicon via dies and packages
Grant 8,586,465 - Liu , et al. November 19, 2
2013-11-19
Packaging Structural Member
App 20130119560 - TOH; Chin Hock ;   et al.
2013-05-16
Vented die and package
Grant 8,426,246 - Toh , et al. April 23, 2
2013-04-23
Mold design and semiconductor package
Grant 8,399,985 - Kolan , et al. March 19, 2
2013-03-19
Packaging structural member
Grant 8,384,203 - Toh , et al. February 26, 2
2013-02-26
Vented Die And Package
App 20120149150 - TOH; Chin Hock ;   et al.
2012-06-14
Interposer For Semiconductor Package
App 20120104628 - TOH; Chin Hock ;   et al.
2012-05-03
Vented die and package
Grant 8,143,719 - Toh , et al. March 27, 2
2012-03-27
Interposer for semiconductor package
Grant 8,115,292 - Toh , et al. February 14, 2
2012-02-14
Mold Design And Semiconductor Package
App 20120018869 - KOLAN; Ravi Kanth ;   et al.
2012-01-26
Mold design and semiconductor package
Grant 8,030,761 - Kolan , et al. October 4, 2
2011-10-04
Stacked die semiconductor package and method of assembly
Grant 7,883,938 - Kolan , et al. February 8, 2
2011-02-08
Structurally-enhanced integrated circuit package and method of manufacture
Grant 7,830,006 - Kolan , et al. November 9, 2
2010-11-09
Interposer For Semiconductor Package
App 20100109142 - Toh; Chin Hock ;   et al.
2010-05-06
Semiconductor Package And Method Of Making The Same
App 20100109169 - KOLAN; Ravi Kanth ;   et al.
2010-05-06
Packaging Structural Member
App 20100013081 - TOH; Chin Hock ;   et al.
2010-01-21
Structurally-enhanced integrated circuit package and method of manufacture
App 20090072391 - Kolan; Ravi Kanth ;   et al.
2009-03-19
Stacked die semiconductor package and method of assembly
App 20090004777 - Kolan; Ravi Kanth ;   et al.
2009-01-01
Vented Die And Package
App 20080303031 - TOH; Chin Hock ;   et al.
2008-12-11
Through Silicon Via Dies And Packages
App 20080303163 - LIU; Hao ;   et al.
2008-12-11
Mold Design And Semiconductor Package
App 20080290505 - KOLAN; Ravi Kanth ;   et al.
2008-11-27
Chip Scale Package and Method of Assembling the Same
App 20080290509 - Tan; Hien Boon ;   et al.
2008-11-27
Method Of Assembling A Silicon Stack Semiconductor Package
App 20080293186 - Hao; Liu ;   et al.
2008-11-27
Thermally enhanced semiconductor package and method of producing the same
App 20070164425 - Kolan; Ravi Kanth ;   et al.
2007-07-19

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