loadpatents
name:-0.0062100887298584
name:-0.021203994750977
name:-0.0033268928527832
Kohli; Vikas Patent Filings

Kohli; Vikas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kohli; Vikas.The latest application filed is for "system and method for facilitating model-based classification of transactions".

Company Profile
3.22.5
  • Kohli; Vikas - Noida IN
  • KOHLI; Vikas - Maharashtra IN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System and method for dynamic visual guidance of mutually paired components in a circuit design editor
Grant 10,606,974 - Acharya , et al.
2020-03-31
System and method for suggesting components associated with an electronic design
Grant 10,289,788 - Kumar , et al.
2019-05-14
Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell
Grant 10,285,276 - Kukal , et al.
2019-05-07
System And Method For Facilitating Model-based Classification Of Transactions
App 20190080248 - KOHLI; Vikas ;   et al.
2019-03-14
System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects
Grant 9,619,605 - Kohli , et al. April 11, 2
2017-04-11
Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabrics
Grant 9,361,415 - Ginetti , et al. June 7, 2
2016-06-07
Method, system, and computer program product for probing or netlisting a multi-fabric electronic design spanning across multiple design fabrics
Grant 9,348,960 - Ginetti , et al. May 24, 2
2016-05-24
Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics
Grant 9,280,621 - Ginetti , et al. March 8, 2
2016-03-08
Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics
Grant 9,223,915 - Ginetti , et al. December 29, 2
2015-12-29
System and method for connecting components in an electronic design
Grant 9,202,006 - Bhattacharya , et al. December 1, 2
2015-12-01
System and method for maintaining dynamic visual cue for associated circuitry of schematic object
Grant 9,122,384 - Kohli , et al. September 1, 2
2015-09-01
Method and system for optimally connecting interfaces across multiple fabrics
Grant 8,527,929 - Bhattacharya , et al. September 3, 2
2013-09-03
Method and system for specifying system level constraints in a cross-fabric design environment
Grant 8,479,134 - Bhattacharya , et al. July 2, 2
2013-07-02
Hierarchical editing of printed circuit board pin assignment
Grant 8,438,524 - Kohli , et al. May 7, 2
2013-05-07
Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout
Grant 8,316,342 - Kukal , et al. November 20, 2
2012-11-20
Method and system for optimally placing and assigning interfaces in a cross-fabric design environment
Grant 8,316,337 - Bhattacharya , et al. November 20, 2
2012-11-20
Pin unspecific device planning for printed circuit board layout
Grant 8,271,933 - Kohli , et al. September 18, 2
2012-09-18
Virtual view schematic editor
Grant 7,990,375 - Kohli , et al. August 2, 2
2011-08-02
Method And System For Specifying System Level Constraints In A Cross-fabric Design Environment
App 20110153289 - BHATTACHARYA; Utpal ;   et al.
2011-06-23
Method And System For Optimally Connecting Interfaces Across Mutiple Fabrics
App 20110153288 - BHATTACHARYA; Utpal ;   et al.
2011-06-23
Method And System For Optimally Placing And Assigning Interfaces In A Cross-fabric Design Environment
App 20110154276 - BHATTACHARYA; Utpal ;   et al.
2011-06-23
Virtual view schematic editor
App 20070229537 - Kohli; Vikas ;   et al.
2007-10-04
Method and apparatus for table and HDL based design entry
Grant 7,168,041 - Durrill , et al. January 23, 2
2007-01-23
Method and apparatus for concurrent engineering and design synchronization of multiple tools
Grant 7,143,341 - Kohli November 28, 2
2006-11-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed