Koh; Hui Peng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Koh; Hui Peng.The latest application filed is for "overlay mark dependent dummy fill to mitigate gate height variation".

Company Profile

0.13.13

Koh; Hui Peng - Gansevoort NY
Koh; Hui Peng - Singapore N/A SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Overlay mark dependent dummy fill to mitigate gate height variation Grant 9,368,453 - Ning , et al. June 14, 2	2016-06-14
Overlay Mark Dependent Dummy Fill To Mitigate Gate Height Variation App 20160079180 - NING; Guoxiang ; et al.	2016-03-17
Overlay mark dependent dummy fill to mitigate gate height variation Grant 9,252,061 - Ning , et al. February 2, 2	2016-02-02
Overlay Mark Dependent Dummy Fill To Mitigate Gate Height Variation App 20150287651 - NING; Guoxiang ; et al.	2015-10-08
Methods for fabricating integrated circuits with improved patterning schemes Grant 8,940,641 - Hu , et al. January 27, 2	2015-01-27
Methods for fabricating EUV masks and methods for fabricating integrated circuits using such EUV masks Grant 8,911,920 - Raghunathan , et al. December 16, 2	2014-12-16
Methods For Fabricating Euv Masks And Methods For Fabricating Integrated Circuits Using Such Euv Masks App 20140272677 - Raghunathan; Sudharshanan ; et al.	2014-09-18
Spacer-less low-K dielectric processes Grant 8,624,329 - Lee , et al. January 7, 2	2014-01-07
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Grant 7,999,325 - Teh , et al. August 16, 2	2011-08-16
Method for reducing silicide defects in integrated circuits Grant 7,960,283 - Ye , et al. June 14, 2	2011-06-14
Integrated circuit system employing sacrificial spacers Grant 7,892,900 - Liu , et al. February 22, 2	2011-02-22
Method For Reducing Silicide Defects In Integrated Circuits App 20100267236 - YE; Jianhui ; et al.	2010-10-21
Method for reducing silicide defects in integrated circuits Grant 7,745,320 - Ye , et al. June 29, 2	2010-06-29
Spacer-less Low-K Dielectric Processes App 20100059831 - Lee; Yong Meng ; et al.	2010-03-11
Method For Reducing Silicide Defects In Integrated Circuits App 20090289309 - YE; Jianhui ; et al.	2009-11-26
Spacer-less low-k dielectric processes Grant 7,615,427 - Lee , et al. November 10, 2	2009-11-10
Integrated Circuit System Employing Sacrificial Spacers App 20090250762 - Liu; Huang ; et al.	2009-10-08
Integrated Circuit System Employing Feed-forward Control App 20090179307 - Zhou; Wenzhan ; et al.	2009-07-16
Method To Remove Spacer After Salicidation To Enhance Contact Etch Stop Liner Stress On Mos App 20090026549 - TEH; Young Way ; et al.	2009-01-29
Semiconductor System Having Complementary Strained Channels App 20080315317 - Lai; Chung Woh ; et al.	2008-12-25
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Grant 7,445,978 - Teh , et al. November 4, 2	2008-11-04
Spacer-less low-k dielectric processes App 20070281410 - Lee; Yong Meng ; et al.	2007-12-06
Composite stress spacer Grant 7,256,084 - Lim , et al. August 14, 2	2007-08-14
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS App 20060249794 - Teh; Young Way ; et al.	2006-11-09
Composite stress spacer App 20060252194 - Lim; Khee Yong ; et al.	2006-11-09

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